ADC08D502 Datasheet, PDF (25/43 Pages) Texas Instruments – ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

ADC08D502
www.ti.com
SNOSC85 – AUGUST 2012
Table 2. Features and Modes
Feature
SDR or DDR Clocking
Normal Control Mode
Selected with pin 4
DDR Clock Phase
Not Selectable (0° Phase Only)
SDR Data transitions with rising or falling
DCLK edge
Selected with pin 4
LVDS output level
Selected with pin 3
Power-On Calibration Delay
Delay Selected with pin 127
Full-Scale Range
Options (650 mV_P-P or 870 mV_P-P) selected
with pin 14. Selected range applies to both
channels.
Input Offset Adjust
Not possible
Extended Control Mode
Selected with DE bit in the Configuration
Register (1h).
Selected with DCP bit in the Configuration
Register (1h).
Selected with the OE bit in the Configuration
Register (1h).
Selected with the OV bit in the Configuration
Register (1h).
Short delay only.
Up to 512 step adjustments over a nominal
range of 560 mV to 840 mV. Separate range
selected for I- and Q-Channels. Selected using
registers 3h and Bh.
Separate ±45 mV adjustments in 512 steps for
each channel using registers 2h and Ah.
The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device)
and is shown in Table 3.
Table 3. Extended Control Mode Operation
(Pin 14 Floating)
Feature
SDR or DDR Clocking
DDR Clock Phase
LVDS Output Amplitude
Calibration Delay
Full-Scale Range
Input Offset Adjust
Extended Control Mode Default State
DDR Clocking
Data changes with DCLK edge (0° phase)
Normal amplitude
(710 mV_P-P)
Short Delay
700 mV nominal for both channels
No adjustment for either channel
THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial interface, all 8 user registers must be written with
desired or default values. In addition, the first write to register (Dh) must load the default value (0x3FFFh). Once
all registers have been written once, other desired settings can be loaded.
The 3-pin serial interface is enabled only when the device is in the Extended Control mode. The pins of this
interface are Serial Clock (SCLK), Serial Data (SDATA) and Serial Interface Chip Select (SCS) Eight write only
registers are accessible through this serial interface.
SCS: This signal should be asserted low while accessing a register through the serial interface. Setup and hold
times with respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of this signal. There is no minimum frequency
requirement for SCLK.
SDATA: Each register access requires a specific 32-bit pattern at this input. This pattern consists of a header,
register address and register value. The data is shifted in MSB first. Setup and hold times with respect to the
SCLK must be observed. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure 5 of the Timing Diagrams. The fixed header pattern
is 0000 0000 0001 (eleven zeros followed by a 1). The loading sequence is such that a 0b is loaded first. These
12 bits form the header. The next 4 bits are the address of the register that is to be written to and the last 16 bits
are the data written to the addressed register. The addresses of the various registers are indicated in Table 4.
Refer to the Register Description for information on the data to be written to the registers.
Copyright © 2012, Texas Instruments Incorporated
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