ADC08D502 Datasheet, PDF (13/43 Pages) Texas Instruments – ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

ADC08D502
www.ti.com
SNOSC85 – AUGUST 2012
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for V_A = V_DR = +1.9V_DC, OutV = 1.9V, V_IN FSR (a.c. coupled) = differential
870mV_P-P, C_L = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f_CLK = 500 MHz at 0.5V_P-P with 50% duty cycle, V_BG =
Floating, Non-Extended Control Mode, SDR Mode, R_EXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits T_A = 25°C, unless otherwise noted. ^{(1) (2)}
Symbol
Parameter
Conditions
Typical
(3)
Limits
(3)
Units
(Limits)
t_WU
f_SCLK
t_SSU
t_SH
PD low to Rated Accuracy Conversion
(Wake-Up Time)
Serial Clock Frequency
(14)
Data to Serial Clock Setup Time
(14)
Data to Serial Clock Hold Time
(14)
Serial Clock Low Time
500
ns
100
MHz
2.5
ns (min)
1
ns (min)
4
ns (min)
t_CAL
t_{CAL_L}
Serial Clock High Time
Calibration Cycle Time
CAL Pin Low Time
See Figure 9 ⁽¹⁵⁾
4
ns (min)
1.4 x 10⁵
Clock Cycles
80
Clock Cycles
(min)
t_{CAL_H}
CAL Pin High Time
See Figure 9 ⁽¹⁵⁾
80
Clock Cycles
(min)
t_CalDly
Calibration delay determined by pin
127
See Figure 9, ⁽¹⁷⁾
2²⁵
Clock Cycles
(min)
t_CalDly
Calibration delay determined by pin
127
See Figure 9, ⁽¹⁷⁾
2³¹
Clock Cycles
(max)
(17) Tying V_BG to the supply rail will increase the output offset voltage (V_OS) by 400mv (typical), as shown in the V_OS specification above.
Tying V_BG to the supply rail will also affect the differential LVDS output voltage (V_OD), causing it to increase by 40mV (typical).
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to
open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode the
aperture delay time (t_AD) after the clock goes low.
APERTURE JITTER (t_AJ) is the variation in aperture delay from sample to sample. Aperture jitter shows up as
input noise.
Bit Error Rate (B.E.R.) is the probability of error and is defined as the probable number of errors per unit of time
divided by the number of bits seen in that amount of time. A B.E.R. of 10^-18 corresponds to a statistical error in
one bit about every four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock wave form is at a logic high to the total time of one
clock period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB. Measured at 500 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion Ratio, or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is a measure of the frequency at which the reconstructed output
fundamental drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Offset and
Full-Scale Errors:
Pos. Gain Error = Offset Error − Pos. Full-Scale Error
Neg. Gain Error = −(Offset Error − Neg. Full-Scale Error)
Gain Error = Neg. Full-Scale Error − Pos. Full-Scale Error = Pos. Gain Error + Neg. Gain Error
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