OMAP3525-HIREL_16 Datasheet, PDF (249/262 Pages) Texas Instruments – OMAP3525-HiRel and OMAP3530-HiRel Applications Processor

OMAP3525-HiRel, OMAP3530-HiRel
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SPRS599D – JUNE 2009 – REVISED AUGUST 2010
6.8 Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs:
• ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time
trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)
• IVA2 DSP through a high-speed real-time data exchange (HS-RTDX) controller
All processors can be emulated via JTAG ports.
6.8.1 Embedded Trace Macro Interface (ETM)
Table 6-142 assumes testing over the recommended operating conditions (see Figure 6-69).
Table 6-142. Embedded Trace Macro Interface Switching Characteristics⁽¹⁾
NO.
PARAMETER
f
1/t_c(CLK)
ETM0 t_c(CLK)
Frequency, etk_clk
Cycle time⁽²⁾, etk_clk
ETM1 t_W(CLK)
Clock pulse width, etk_clk
ETM2 t_d(CLK-CTL)
Delay time, etk_clk clock edge to etk_ctl transition
ETM3 t_d(CLK-D)
Delay time, etk_clk clock high to etk_d[15:0] transition
(1) The capacitive load is equivalent to 25 pF.
(2) Cycle time is given by considering a jitter of 5%.
1.15 V
MIN
MAX
166
6
2.7
–0.5
0.5
–0.5
0.5
UNIT
MHz
ns
ns
ns
ns
etk_clk
etk_ctl
etk_d[15:0]
ETM2
ETM0
ETM1
ETM3
ETM3
Figure 6-69. Embedded Trace Macro Interface
ETM2
030-110
6.8.2 System Debug Trace Interface (SDTI)
The system debug trace interface (SDTI) module provides real-time software tracing functionality to the
OMAP3525 and OMAP3530 device.
The trace interface has four trace data pins and a trace clock pin.
This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can
be also configured in single edge mode where data are available on falling edge of sdti_clk.
Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data
there is no trace clock.
6.8.2.1 System Debug Trace Interface in Dual-Edge Mode
Table 6-144 assumes testing over the recommended operating conditions and electrical characteristic
conditions (see Figure 6-70).
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 249
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