OMAP3525-HIREL_16 Datasheet, PDF (197/262 Pages) Texas Instruments – OMAP3525-HiRel and OMAP3530-HiRel Applications Processor

www.ti.com
dss_pclk
DL5
DL4
OMAP3525-HiRel, OMAP3530-HiRel
SPRS599D – JUNE 2009 – REVISED AUGUST 2010
dss_vsync
dss_hsync
dss_acbias
DL3
dss_data[23:0]
030-062
Figure 6-29. LCD Display in STN Mode(1) (2) (3) (4) (5)
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(3) dss_vsync width must be programmed to be as small as possible.
(4) The pixel clock frequency is programmable.
(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98 .
6.5.2.2 LCD Display in RFBI Mode
Table 6-40 and Table 6-41 assume testing over the recommended operating conditions (see Figure 6-30
through Figure 6-32).
Table 6-39. LCD Timing Conditions – RFBI Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Conditions
C_LOAD
Output load capacitance
VALUE
MIN
MAX
15
15
30
UNIT
ns
ns
pF
Table 6-40. LCD Display Timing Requirements in RFBI Mode
NO.
PARAMETER
OPP3
MIN MAX
DR0 t_su(DAV-RDH) Setup time, rfbi_da[15:0] valid to rfbi_rd
7.0
high
DR1
t_h(RDH-DAIV)
t_{d(Data sampled)}
Hold time, rfbi_rd high to rfbi_da[15:0]
invalid
rfbi_da[15:0] are sampled at the end off
the access time
5.0
N⁽²⁾
(1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.
(2) N = (AccessTime) * (TimeParaGranularity + 1) * L4CLK
OPP2
MIN MAX
9.0
5.0
N⁽²⁾
OPP1⁽¹⁾
MIN MAX
UNIT
ns
ns
ns
Copyright © 2009–2010, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 197
Submit Documentation Feedback
Product Folder Link(s): OMAP3525-HiRel OMAP3530-HiRel