OMAP3525-HIREL_16 Datasheet, PDF (243/262 Pages) Texas Instruments – OMAP3525-HiRel and OMAP3530-HiRel Applications Processor

OMAP3525-HiRel, OMAP3530-HiRel
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SPRS599D – JUNE 2009 – REVISED AUGUST 2010
Table 6-133. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode^{(1) (2) (3)}
NO.
PARAMETER
1.15 V
1.0 V
MIN
MAX
MIN
MAX
High-Speed SD Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
HSSD3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
5.6
26
mmc1_clk rising clock edge
HSSD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after mmc1_clk
2.3
1.9
rising clock edge
HSSD7 t_{su(DATxV-CLKIH)}
Setup time, mmc1_datx valid before
5.6
26
mmc1_clk rising clock edge
HSSD8 t_{su(CLKIH-DATxIV)}
Hold time, mmc1_datx valid after mmc1_clk
2.3
1.9
rising clock edge
MMC/SD/SDIO Interface 1 (3.0 V IO)
HSSD3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
5.6
26
mmc1_clk rising clock edge
HSSD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after mmc1_clk
2.3
1.9
rising clock edge
HSSD7 t_{su(DATxV-CLKIH)}
Setup time, mmc1_datx valid before
5.6
26
mmc1_clk rising clock edge
HSSD8 t_{su(CLKIH-DATxIV)}
Hold time, mmc1_datx valid after mmc1_clk
2.3
1.9
rising clock edge
MMC/SD/SDIO Interface 2
HSSD3 t_{su(CMDV-CLKIH)}
Setup time, mmc2_cmd valid before
5.6
26
mmc2_clk rising clock edge
HSSD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc2_cmd valid after mmc2_clk
2.3
1.9
rising clock edge
HSSD7 t_{su(DATxV-CLKIH)}
Setup time, mmc2_datx valid before
5.6
26
mmc2_clk rising clock edge
HSSD8 t_{su(CLKIH-DATxIV)}
Hold time, mmc2_datx valid after mmc2_clk
2.3
1.9
rising clock edge
MMC/SD/SDIO Interface 3
HSSD3 t_{su(CMDV-CLKIH)}
Setup time, mmc3_cmd valid before
5.6
26
mmc3_clk rising clock edge
HSSD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc3_cmd valid after mmc3_clk
2.3
1.9
rising clock edge
HSSD7 t_{su(DATxV-CLKIH)}
Setup time, mmc3_datx valid before
5.6
26
mmc3_clk rising clock edge
HSSD8 t_{su(CLKIH-DATxIV)}
Hold time, mmc3_datx valid after mmc3_clk
2.3
1.9
rising clock edge
(1) Timing Parameters are referred to output clock specified in Table 6-134.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-134.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode
NO.
PARAMETER
High-Speed SD Mode
1/HSSD 1/t_c(clk)
1
HSSD2 t_W(clkH)
Frequency⁽¹⁾, mmcx_ clk ⁽²⁾
Typical pulse duration, output clk high
1.15 V
MIN
MAX
1.0 V
MIN
MAX
48
24
X ⁽³⁾*PO ⁽⁴⁾
X ⁽³⁾*PO ⁽⁴⁾
UNIT
ns
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.
(3) The X parameter is defined as shown in Table 6-135.
(4) PO = output clk period in ns.
Copyright © 2009–2010, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 243
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