TM4C1231H6PM Datasheet, PDF (245/1146 Pages) Texas Instruments – Tiva™ TM4C1231H6PM Microcontroller

Tiva^™ TM4C1231H6PM Microcontroller
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 10-6 on page 625).
Important: Ports K-N and P-Q are only available on the AHB bus, and therefore the corresponding
bits reset to 1. If one of these bits is cleared, the corresponding port is disabled. If any
of these ports is in use, read-modify-write operations should be used to change the
value of this register so that these ports remain enabled.
GPIO High-Performance Bus Control (GPIOHBCTL)
Base 0x400F.E000
Offset 0x06C
Type RW, reset 0x0000.7E00
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
reserved
RO
RO
0
0
8
7
RO
RO
0
0
22
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
6
5
4
3
2
1
0
PORTF PORTE PORTD PORTC PORTB PORTA
RO
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
PORTF
Type
RO
RW
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Port F Advanced High-Performance Bus
This bit defines the memory aperture for Port F.
Value Description
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
4
PORTE
RW
0
Port E Advanced High-Performance Bus
This bit defines the memory aperture for Port E.
Value Description
0 Advanced Peripheral Bus (APB). This bus is the legacy bus.
1 Advanced High-Performance Bus (AHB)
June 12, 2014
245
Texas Instruments-Production Data