TM4C1231H6PM Datasheet, PDF (169/1146 Pages) Texas Instruments – Tiva™ TM4C1231H6PM Microcontroller

Tiva^™ TM4C1231H6PM Microcontroller
Bit/Field
17
16
15
14
13
Name
INVSTAT
UNDEF
BFARV
reserved
BLSPERR
Type
RW1C
RW1C
RW1C
RO
RW1C
Reset
0
0
0
0
0
Description
Invalid State Usage Fault
Value Description
0 A usage fault has not been caused by an invalid state.
1 The processor has attempted to execute an instruction that
makes illegal use of the EPSR register.
When this bit is set, the PC value stacked for the exception return points
to the instruction that attempted the illegal use of the Execution
Program Status Register (EPSR) register.
This bit is not set if an undefined instruction uses the EPSR register.
This bit is cleared by writing a 1 to it.
Undefined Instruction Usage Fault
Value Description
0 A usage fault has not been caused by an undefined instruction.
1 The processor has attempted to execute an undefined
instruction.
When this bit is set, the PC value stacked for the exception return points
to the undefined instruction.
An undefined instruction is an instruction that the processor cannot
decode.
This bit is cleared by writing a 1 to it.
Bus Fault Address Register Valid
Value Description
0 The value in the Bus Fault Address (FAULTADDR) register
is not a valid fault address.
1 The FAULTADDR register is holding a valid fault address.
This bit is set after a bus fault, where the address is known. Other faults
can clear this bit, such as a memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority,
the hard fault handler must clear this bit. This action prevents problems
if returning to a stacked active bus fault handler whose FAULTADDR
register value has been overwritten.
This bit is cleared by writing a 1 to it.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Bus Fault on Floating-Point Lazy State Preservation
Value Description
0 No bus fault has occurred during floating-point lazy state
preservation.
1 A bus fault has occurred during floating-point lazy state
preservation.
This bit is cleared by writing a 1 to it.
June 12, 2014
169
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