TM4C1231H6PM Datasheet, PDF (14/1146 Pages) Texas Instruments – Tiva™ TM4C1231H6PM Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 1-1.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Revision History .................................................................................................. 32
Documentation Conventions ................................................................................ 37
TM4C1231H6PM Microcontroller Features ............................................................ 40
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 64
Processor Register Map ....................................................................................... 65
PSR Register Combinations ................................................................................. 71
Memory Map ....................................................................................................... 82
Memory Access Behavior ..................................................................................... 85
SRAM Memory Bit-Banding Regions .................................................................... 87
Peripheral Memory Bit-Banding Regions ............................................................... 87
Exception Types .................................................................................................. 93
Interrupts ............................................................................................................ 94
Exception Return Behavior ................................................................................. 101
Faults ............................................................................................................... 102
Fault Status and Fault Address Registers ............................................................ 103
Cortex-M4F Instruction Summary ....................................................................... 105
Core Peripheral Register Regions ....................................................................... 112
Memory Attributes Summary .............................................................................. 116
TEX, S, C, and B Bit Field Encoding ................................................................... 118
Cache Policy for Memory Attribute Encoding ....................................................... 119
AP Bit Field Encoding ........................................................................................ 119
Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 120
QNaN and SNaN Handling ................................................................................. 123
Peripherals Register Map ................................................................................... 124
Interrupt Priority Levels ...................................................................................... 154
Example SIZE Field Values ................................................................................ 182
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 191
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 192
JTAG Instruction Register Commands ................................................................. 198
System Control & Clocks Signals (64LQFP) ........................................................ 202
Reset Sources ................................................................................................... 203
Clock Source Options ........................................................................................ 210
Possible System Clock Frequencies Using the SYSDIV Field ............................... 212
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 213
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 213
System Control Register Map ............................................................................. 220
RCC2 Fields that Override RCC Fields ............................................................... 247
System Exception Register Map ......................................................................... 450
Hibernate Signals (64LQFP) ............................................................................... 459
Hibernation Module Clock Operation ................................................................... 468
Hibernation Module Register Map ....................................................................... 470
Flash Memory Protection Policy Combinations .................................................... 494
User-Programmable Flash Memory Resident Registers ....................................... 498
Flash Register Map ............................................................................................ 505
μDMA Channel Assignments .............................................................................. 552
Request Type Support ....................................................................................... 554
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June 12, 2014
Texas Instruments-Production Data