OPA180-Q1 Datasheet, PDF (24/32 Pages) Texas Instruments – 0.1-uV/C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero-Drift Operational Amplifiers

OPA180-Q1, OPA2180-Q1
SBOS861 – MAY 2017
11 Layout
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11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the
analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep the input traces separate, it is much better to cross the sensitive
trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 35, keeping RF
and RG close to the inverting inputminimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RG
GND
RF
N/C
±IN
VS+
N/C
Use a low-ESR,
ceramic bypass
V+
capacitor
VIN
+IN
OUTPUT
V±
N/C
GND
VS±
Use low-ESR,
ceramic bypass
capacitor
GND
VOUT
Ground (GND) plane on another layer
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Operational Amplifier Board Layout for Noninverting Configuration
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