DRV3203-Q1 Datasheet, PDF (24/39 Pages) Texas Instruments – DRV3203-Q1 Three-Phase Brushless Motor Driver

Not Recommended for New Designs
DRV3203-Q1
SLVSC09B – MAY 2013 – REVISED JULY 2016
Feature Description (continued)
VDD
VCC
VCC
Level Shift
EN
DOUT
Figure 21. Output Buffer2 Block Diagram
VDD
VCC
Level Shift
VCC
VCC
R_RES
RES
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Figure 22. Output Buffer3 Block Diagram
7.2.12 Fault Detection
Table 1. Recommended Pin Termination
PIN NAME
TEST
DESCRIPTION
Test mode input
TERMINATION
OPEN
ITEMS
VB - Overvoltage
VB - Undervoltage
CP - Overvoltage
CP - Undervoltage
VCC - Overvoltage
VCC - Under Voltage
VCC - Overcurrent
Motor - Overcurrent
VDD - Overvoltage
VDD - Undervoltage
Thermal shutdown
Watch Dog
Clock Monitor
SPI format error
SPI FLTFLG
VBOV
VBUV
CPOV
CPUV
VCCOV
-
VCCOC
MTOC
VDDOV
-
TSD
-
-
-
Table 2. Fault Detection
Pre Driver⁽¹⁾
FAULT ⁽²⁾
Disable
L
Disable
L
Disable
L
Disable
L
Disable
L
Disable ⁽³⁾
H
Disable
L
Disable
L
Disable
L
Disable ⁽³⁾
H
Disable
L
-
H
-
H
-
H
RES
H
H
H
H
H
L
H
H
H
L
H
L
L
H
Others
SPI serial out error bit
(1) Pre-driver is disabled if the conditions occur and SDNEN register bits are 1.
(2) FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1.
(3) Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.
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