DRV3203-Q1 Datasheet, PDF (23/39 Pages) Texas Instruments – DRV3203-Q1 Three-Phase Brushless Motor Driver

Not Recommended for New Designs
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DRV3203-Q1
SLVSC09B – MAY 2013 – REVISED JULY 2016
Feature Description (continued)
7.2.10 Oscillator
The oscillator block generates two 10-MHZ clock signals. OSC1 is the primary clock used for internal logic-
synchronization and timing control. OSC2 is the secondary clock used to monitor the status of OSC1.
VREF
OSC1(OSC2)
Figure 18. Oscillator Block Diagram
7.2.11 I/O
VCC
VDD
VDD
DIN
SCK
CTLxx
TEST
Level Shift
Rd
VCC
VCC
VDD
CS
PRN
Ru
Level Shift
VDD
ENABLE
CLAMP
V5INT
Rd
V5INT
* V5INT is the internal power supply.
Figure 19. Input Buffer1 Block Diagram
VDD
VCC
VCC
Level Shift
FAULT
Figure 20. Output Buffer1 Block Diagram
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