DRV2605L-Q1 Datasheet, PDF (24/67 Pages) Texas Instruments – Automotive Haptic Driver for LRA and ERM

DRV2605L-Q1
SLOS874A – OCTOBER 2015 – REVISED OCTOBER 2015
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Programming (continued)
7.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DRV2605L-Q1 device as shown in Figure 21. After receiving each
data byte, the DRV2605L-Q1 device responds with an acknowledge bit.
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A1 A0
A1 A0 W ACK A7 A6
A1 A0 ACK D7 D6
D1 D0 ACK D7
D0 ACK D7
D0 ACK
Start
condition
I²C device address
and R/W bit
Subaddress
First data byte
Other data bytes
Last data byte
Stop
condition
Figure 21. Multiple-Byte Write Transfer
7.5.3.5 Single-Byte Read
Figure 22 shows that a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I²C device address and the read-write bit. For the data-read transfer, both a write followed by a
read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be
read. As a result, the read-write bit is set to 0.
After receiving the DRV2605L-Q1 address and the read-write bit, the DRV2605L-Q1 device responds with an
acknowledge bit. The master then sends the internal memory address byte, after which the device issues an
acknowledge bit. The master device transmits another start condition followed by the DRV2605L-Q1 address and
the read-write bit again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2605L-
Q1 device transmits the data byte from the memory address that is read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read
transfer. See the note in the General I²C Operation section.
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A6 A5
A1 A0 W ACK A7 A6
A1 A0 ACK
A6 A5
A0 R ACK D7
D0 ACK
Start
Condition
2
I C device address and
R/W bit
Subaddress
Repeat start
2
I C device address and
condition
R/W bit
Figure 22. Single-Byte Read Transfer
Data Byte
Stop
Condition
7.5.3.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the DRV2605L-Q1 device to the master device as shown in Figure 23. With the exception of
the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Acknowledge
Acknowledge
Acknowledge Acknowledge Acknowledge Acknowledge
A6
A0 W ACK A7 A6
A1 A0 ACK
A6 A5 A0 R ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
Start _I²_{C device address}
condition _{and R/W bit}
Subaddress
Repeat start
2
I C device address
condition
and R/W bit
First data byte Other data byte Last data byte
Figure 23. Multiple-Byte Read Transfer
Stop
condition
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