ADS8556 Datasheet, PDF (24/47 Pages) Texas Instruments – 16-14-12-Bit Six-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

ADS8556, ADS8557, ADS8558
SBAS404D – OCTOBER 2006 – REVISED FEBRUARY 2016
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7.3 Feature Description
7.3.1 Analog
This section addresses the analog input circuit, the ADCs and control signals, and the reference design of the
device.
7.3.1.1 Analog Inputs
The inputs and the converters are of single-ended, bipolar type. The absolute voltage range can be selected
using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR) to
either ±4 V_REF or ±2 V_REF. With the reference set to 2.5 V (CR bit C18 = 0), the input voltage range can be ±10 V
or ±5 V. With the reference source set to 3 V (CR bit C18 = 1), an input voltage range of ±12 V or ±6 V can be
configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 = 0).
The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source
impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the
sampling period (t_ACQ). The source of the analog input voltage must be able to charge the input capacitance of
10 pF in ±4-V_REF mode or 20 pF in ±2-V_REF to a 12-, 14-, 16-bit accuracy level within the acquisition time of 280
ns at maximum data rate; see Figure 1. During the conversion period, there is no further input current flow and
the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the
ADS855x are pre-charged to a fixed internal voltage before switching into sampling mode.
To maintain the linearity of the converter, the inputs must always remain within the specified range of HVSS –
0.2 V to HVDD + 0.2 V.
The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:
ln(2) ´ (n + 1)
f_-3dB =
2p ´ t_ACQ
where
• n = 16, 14, or 12; n is the resolution of the ADS855x
(1)
With a minimum acquisition time of t_ACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 6.7
MHz for the ADS8556, 6 MHz for the ADS8557, or 5.2 MHz for the ADS8558. The required bandwidth can be
lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill
the bandwidth requirement shown in Equation 1.
A driving operational amplifier may not be required if the impedance of the signal source (R_SOURCE) fulfills the
requirement of Equation 2:
R_SOURCE <
t_ACQ
C_S ln(2) ´ (n + 1)
- (R_SER + R_SW)
where
• n = 16, 14, or 12; n is the resolution of the ADC
• C_S = 10 pF is the sample capacitor value for V_IN = ±4 × V_REF mode
• R_SER = 200 Ω is the input resistor value
• R_SW = 130 Ω is the switch resistance value
(2)
With t_ACQ = 280 ns, the maximum source impedance must be less than 2.0 kΩ for the ADS8556, 2.3 kΩ for the
ADS8557, and 2.7 kΩ for the ADS8558 in V_IN = ±4 V_REF mode or less than 0.8 kΩ for the ADS8556, 1.0 kΩ for
the ADS8557, and 1.2 kΩ for the ADS8558 in V_IN = ±2 V_REF mode. The source impedance can be higher if the
application allows longer acquisition time.
7.3.1.2 Analog-to-Digital Converter (ADC)
The devices include six ADCs that operate with either an internal or an external conversion clock. The
conversion time can be as low as 1.09 μs with an internal conversion clock (ADS8558). When an external clock
and reference are used, the minimum conversion time is 925 ns.
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