LM3S5U91 Datasheet, PDF (238/1339 Pages) Texas Instruments – Stellaris® LM3S5U91 Microcontroller

System Control
Bit/Field
15:12
11:10
9:8
7
6
5
4
3
2
1
Name
MINSYSDIV
MAXADC1SPD
MAXADC0SPD
MPU
reserved
TEMPSNS
PLL
WDT0
SWO
SWD
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
-
Description
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x1 Specifies an 80-MHz CPU clock with a PLL divider of 2.5.
0x2 Specifies a 66.67-MHz CPU clock with a PLL divider of 3.
0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x7 Specifies a 25-MHz clock with a PLL divider of 8.
0x9 Specifies a 20-MHz clock with a PLL divider of 10.
0x3
Max ADC1 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3 1M samples/second
0x3
Max ADC0 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3 1M samples/second
1
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the "Cortex-M3 Peripherals" chapter for details
on the MPU.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
1
Watchdog Timer 0 Present
When set, indicates that watchdog timer 0 is present.
1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
238
January 23, 2012
Texas Instruments-Production Data