LM3S5U91 Datasheet, PDF (100/1339 Pages) Texas Instruments – Stellaris® LM3S5U91 Microcontroller

The Cortex-M3 Processor
2.5.5
Figure 2-6. Vector Table
Exception number IRQ number Offset
Vector
70
54
IRQ54
0x0118
.
.
.
.
.
.
.
.
.
0x004C
18
2
IRQ2
0x0048
17
1
IRQ1
0x0044
16
0
IRQ0
0x0040
15
-1
Systick
0x003C
14
-2
PendSV
0x0038
13
Reserved
12
Reserved for Debug
11
-5
SVCall
0x002C
10
9
Reserved
8
7
6
-10
Usage fault
0x0018
5
-11
Bus fault
0x0014
4
-12
Memory management fault
0x0010
3
-13
Hard fault
0x000C
2
-14
NMI
0x0008
1
Reset
0x0004
Initial SP value
0x0000
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000.0200 to 0x3FFF.FE00 (see “Vector Table” on page 99). Note
that when configuring the VTABLE register, the offset must be aligned on a 512-byte boundary.
Exception Priorities
As Table 2-8 on page 97 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 151 and
page 135.
Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means
that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always
have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
100
January 23, 2012
Texas Instruments-Production Data