LM3S5U91 Datasheet, PDF (1183/1339 Pages) Texas Instruments – Stellaris® LM3S5U91 Microcontroller

Stellaris^® LM3S5U91 Microcontroller
Table 23-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PH2
I/O
TTL
GPIO port H bit 2.
C1o
O
TTL
Analog comparator 1 output.
84
EPI0S1
I/O
TTL
EPI module 0 signal 1.
Fault3
I
TTL
PWM Fault 3.
IDX1
I
TTL
QEI module 1 index.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
85
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PH0
I/O
TTL
GPIO port H bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
86
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PJ1
I/O
TTL
GPIO port J bit 1.
EPI0S17
I/O
TTL
EPI module 0 signal 17.
87
I2C1SDA
I/O
OD
I²C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
USB0PFLT
I
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
VDDC
88
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 25-6 on page 1258.
PB7
I/O
TTL
GPIO port B bit 7.
89
NMI
I
TTL
Non-maskable interrupt.
PB6
I/O
TTL
GPIO port B bit 6.
C0+
I
Analog Analog comparator 0 positive input.
C0o
O
TTL
Analog comparator 0 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
90
Fault1
I
TTL
PWM Fault 1.
I2S0TXSCK
I/O
TTL
I²S module 0 transmit clock.
IDX0
I
TTL
QEI module 0 index.
VREFA
I
Analog This input provides a reference voltage used to specify the input
voltage at which the ADC converts to a maximum value. In other
words, the voltage that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA input is limited
to the range specified in Table 25-23 on page 1269 .
January 23, 2012
Texas Instruments-Production Data
1183