DM3730_14 Datasheet, PDF (237/281 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
The I²C controller supports the multi-master mode which allows more than one device capable of
controlling the bus to be connected to it. Each I²C device is recognized by a unique address and can
operates as either transmitter or receiver, according to the function of the device. In addition to being a
transmitter or receiver, a device connected to the I²C bus can also be considered as master or slave when
performing data transfers. This data transfer is carried out via two serial bidirectional wires:
• An SDA data line
• An SCL clock line
In Figure 6-53 the data transfer is in master or slave configuration with 7-bit addressing format.
The I²C interface is compliant with Philips I²C specification version 2.1. It supports standard mode (up to
100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s).
6.6.5.1 I²C—Standard and Fast Modes
Table 6-97. I²C—Standard and Fast Modes
NO.
PARAMETER
STANDARD MODE
FAST MODE
UNIT
MIN
MAX
MIN
MAX
f_scl
Frequency, clock i2cx_scl⁽⁴⁾
100
400
kHz
I1
t_w(sclH)
Pulse duration, clock i2cx_scl⁽⁴⁾ high
4.0
0.6
μs
I2
t_w(sclL)
Pulse duration, clock i2cx_scl⁽⁴⁾ low
4.7
1.3
μs
I3
t_{su(sdaV-sclH)}
Setup time, data i2cx_sda⁽⁴⁾ valid before clock
250
100⁽¹⁾
ns
i2cx_scl⁽⁴⁾ active level
I4
t_h(sclH-sdaV)
Hold time, data i2cx_sda⁽⁴⁾ valid after clock
i2cx_scl⁽⁴⁾ active level
0⁽²⁾
3.45⁽³⁾
0⁽²⁾
0.9⁽³⁾
μs
I5
t_{su(sdaL-sclH)}
Setup time, clock i2cx_scl⁽⁴⁾ high after data
4.7
0.6
μs
i2cx_sda⁽⁴⁾ low (for a START⁽⁵⁾ condition or a
repeated START condition)
I6
t_h(sclH-sdaH)
Hold time, data i2cx_sda low level after clock
4.0
0.6
μs
i2cx_scl⁽⁴⁾ high level (STOP condition)
I7
t_{h(sclH-RSTART)} Hold time, data i2cx_sda⁽⁴⁾ low level after
4.0
0.6
μs
clock i2cx_scl⁽⁴⁾ high level (for a repeated
START condition)
I8
t_w(sdaH)
Pulse duration, data i2cx_sda⁽⁴⁾ high between
4.7⁽⁴⁾
1.3
μs
STOP and START conditions
t_R(scl)
t_F(scl)
t_R(sda)
t_F(sda)
Rise time, clock i2cx_scl⁽⁴⁾
Fall time, clock i2cx_scl⁽⁴⁾
Rise time, data i2cx_sda⁽⁴⁾
Fall time, data i2cx_sda⁽⁴⁾
1000
20 +
300
ns
0.1C_B
300
20 +
300
ns
0.1C_B
1000
20 +
300
ns
0.1C_B
300
20 +
300
ns
0.1C_B
C_B
Capacitive load for each bus line
400
400
pF
(1) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_{su(SDAV-SCLH)} ≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl⁽⁴⁾. If such a device does stretch the low
period of the i2cx_scl⁽⁴⁾, it must output the next data bit to the i2cx_sda⁽⁴⁾ line t_r(SDA) max + t_{su(SDAV-SCLH)} = 1000 + 250 = 1250 ns
(according to the standard-mode I²C-bus specification) before the i2cx_scl⁽⁴⁾ line is released.
(2) The device provides (via the I²C bus) a minimum hold time (= I2C_FCLK period x (PSC+1) x 4) for the i2cx_sda⁽⁴⁾ signal (see the fall
and rise times of i2cx_scl⁽⁴⁾) to bridge the undefined region of the falling edge of i2cx_scl⁽⁴⁾.
(3) The maximum t_h(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl⁽⁴⁾ signal.
(4) In i2cx, x is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(5) After this time, the first clock is generated.
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Timing Requirements and Switching Characteristics 237
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