DM3730_14 Datasheet, PDF (161/281 Pages) Texas Instruments – Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
Table 6-4. GPMC/NOR Flash Switching Characteristics—Synchronous Mode^{(2) (18)} (continued)
NO.
t_dc(clk)
t_J(clk)
t_R(clk)
t_F(clk)
t_R(do)
t_F(do)
F2
t_d(clkH-ncsV)
F3
t_{d(clkH-ncsIV)}
F4
t_d(aV-clk)
F5
t_d(clkH-aIV)
F6
t_d(nbeV-clk)
F7
t_{d(clkH-nbeIV)}
F8
t_d(clkH-nadv)
F9
t_{d(clkH-nadvIV)}
F10
F11
F14
F15
F17
t_d(clkH-noe)
t_{d(clkH-noeIV)}
t_d(clkH-nwe)
t_d(clkH-do)
t_d(clkH-nbe)
F18
t_w(ncsV)
F19
t_w(nbeV)
F20
t_w(nadvV)
F23
t_{d(clkH-iodir)}
F24
t_{d(clkH-iodirIV)}
PARAMETER
OPP100
OPP50
MIN
MAX
MIN
MAX
Duty cycle error, output clock gpmc_clk
Jitter standard deviation⁽¹⁶⁾, output clock gpmc_clk
–500
500
33.33
–500
500
33.33
Rise time, output clock gpmc_clk
1.6
1.6
Fall time, output clock gpmc_clk
1.6
1.6
Rise time, output data gpmc_d[15:0]
2
2
Fall time, output data gpmc_d[15:0]
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_ncsx⁽¹¹⁾ transition
Delay time, output clock gpmc_clk rising edge to
output chip select gpmc_ncsx⁽¹¹⁾ invalid
Delay time, output address gpmc_a[27:1] valid to
output clock gpmc_clk first edge
2
2
F⁽⁶⁾ – 1.9 F⁽⁶⁾ + 3.3 F⁽⁶⁾ – 1.9 F⁽⁶⁾ + 3.3
E⁽⁵⁾ – 1.9 E⁽⁵⁾ + 3.3 E⁽⁵⁾ – 1.9 E⁽⁵⁾ + 3.3
B⁽²⁾ – 4.1 B⁽²⁾ + 2.1 B⁽²⁾ – 4.1 B⁽²⁾ + 2.1
Delay time, output clock gpmc_clk rising edge to
output address gpmc_a[27:1] invalid
Delay time, output lower byte enable/command latch
enable gpmc_nbe0_cle, output upper byte enable
gpmc_nbe1 valid to output clock gpmc_clk first edge
Delay time, output clock gpmc_clk rising edge to
output lower byte enable/command latch enable
gpmc_nbe0_cle, output upper byte enable gpmc_nbe1
invalid
Delay time, output clock gpmc_clk rising edge to
output address valid/address latch enable
gpmc_nadv_ale transition
Delay time, output clock gpmc_clk rising edge to
output address valid/address latch enable
gpmc_nadv_ale invalid
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_noe transition
Delay time, output clock gpmc_clk rising edge to
output enable gpmc_noe invalid
Delay time, output clock gpmc_clk rising edge to
output write enable gpmc_nwe transition
Delay time, output clock gpmc_clk rising edge to
output data gpmc_d[15:0] transition
Delay time, output clock gpmc_clk rising edge to
output lower byte enable/command latch enable
gpmc_nbe0_cle transition
Pulse duration, output chip select
gpmc_ncsx⁽¹¹⁾ low
Read
Write
Pulse duration, output lower byte
enable/command latch enable
gpmc_nbe0_cle, output upper byte enable
gpmc_nbe1 low
Read
Write
Pulse duration, output address
Read
valid/address latch enable gpmc_nadv_ale
low
Write
Delay time, output clock gpmc_clk rising edge to
output IO direction control gpmc_io_dir high (IN
direction)
Delay time, output clock gpmc_clk rising edge to
output IO direction control gpmc_io_dir low (OUT
direction)
–2.1
B⁽²⁾ – 1.2 B⁽²⁾ + 2.2
D⁽⁴⁾ – 2.2 D⁽⁴⁾ + 1.2
G⁽⁷⁾ + 0.8 G⁽⁷⁾ + 2.2
D⁽⁴⁾ – 1.9 D⁽⁴⁾ + 4.1
H⁽⁸⁾ – 2.1 H⁽⁸⁾ + 2.1
E⁽⁵⁾ – 2.1 E⁽⁵⁾ + 2.1
I⁽⁹⁾ – 1.9 I⁽⁹⁾ + 4.1
J⁽¹⁰⁾ –
1.7
J⁽¹⁰⁾ –
2.2
J⁽¹⁰⁾ +
1.2
J⁽¹⁰⁾ +
1.2
A⁽¹⁾
A⁽¹⁾
C⁽³⁾
C⁽³⁾
K⁽¹³⁾
K⁽¹³⁾
H⁽⁸⁾ – 2.1 H⁽⁸⁾ + 4.1
M⁽¹⁷⁾ –
2.1
M⁽¹⁷⁾ +
4.1
–2.1
B⁽²⁾ – 1.2 B⁽²⁾ + 2.2
D⁽⁴⁾ – 2.2 D⁽⁴⁾ + 1.2
G⁽⁷⁾ + 0.8 G⁽⁷⁾ + 2.2
D⁽⁴⁾ – 1.9 D⁽⁴⁾ + 4.1
H⁽⁸⁾ – 2.1 H⁽⁸⁾ + 2.1
E⁽⁵⁾ – 2.1 E⁽⁵⁾ + 2.1
I⁽⁹⁾ – 1.9 I⁽⁹⁾ + 4.1
J⁽¹⁰⁾ –
1.7
J⁽¹⁰⁾ –
2.2
J⁽¹⁰⁾ +
1.2
J⁽¹⁰⁾ +
1.2
A⁽¹⁾
A⁽¹⁾
C⁽³⁾
C⁽³⁾
K⁽¹³⁾
K⁽¹³⁾
H⁽⁸⁾ – 2.1 H⁽⁸⁾ + 4.1
M⁽¹⁷⁾ –
2.1
M⁽¹⁷⁾ +
4.1
UNIT
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 161
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