TMS320DM6433 Datasheet, PDF (231/271 Pages) Texas Instruments – Digital Media Processor

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HEX ADDRESS RANGE
01D0 10CC – 01D0 10FC
01D0 1100
01D0 1104
01D0 1108
01D0 110C
01D0 1110
01D0 1114
01D0 1118
01D0 111C
01D0 1120
01D0 1124
01D0 1128
01D0 112C
01D0 1130
01D0 1134
01D0 1138
01D0 113C
01D0 1140
01D0 1144
01D0 1148
01D0 114C
01D0 1150
01D0 1154
01D0 1158
01D0 115C
01D0 1160 – 01D0 117C
01D0 1180
01D0 1184
01D0 1188
01D0 118C
01D0 1190 – 01D0 11FC
01D0 1200
01D0 1204
01D0 1208
01D0 120C
01D0 1210 – 01D0 127C
01D0 1280
01D0 1284
01D0 1288
01D0 128C
01D0 1290 – 01D0 13FF
TMS320DM6433
Digital Media Processor
SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-61. McASP0 Control Registers (continued)
ACRONYM
–
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
–
SRCTL0
SRCTL1
SRCTL2
SRCTL3
–
XBUF0
XBUF1
XBUF2
XBUF3
–
RBUF0
RBUF1
RBUF2
RBUF3
–
REGISTER NAME
Reserved
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Reserved
Serializer 0 control register
Serializer 1 control register
Serializer 2 control register
Serializer 3 control register
Reserved
Transmit Buffer for Serializer 0
Transmit Buffer for Serializer 1
Transmit Buffer for Serializer 2
Transmit Buffer for Serializer 3
Reserved
Receive Buffer for Serializer 0
Receive Buffer for Serializer 1
Receive Buffer for Serializer 2
Receive Buffer for Serializer 3
Reserved
HEX ADDRESS RANGE
01D0 1400 – 01D0 17FF
Table 6-62. McASP0 Data Registers
ACRONYM
REGISTER NAME
RBUF/XBUF
McASP0 receive buffers or McASP0 transmit buffers via
the Peripheral Data Bus.
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT registers,
respectively].)
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Peripheral Information and Electrical Specifications 231