OPA333_17 Datasheet, PDF (23/42 Pages) Texas Instruments – 1.8-V, microPower, CMOS Operational Amplifiers, Zero-Drift Series

www.ti.com
10 Layout
OPA333, OPA2333
SBOS351E – MARCH 2006 – REVISED DECEMBER 2015
10.1 Layout Guidelines
10.1.1 General Layout Guidelines
Pay attention to good layout practices. Keep traces short and when possible, use a printed-circuit-board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-μF
capacitor closely across the supply pins. Apply these guidelines throughout the analog circuit to improve
performance and provide benefits, such as reducing the electromagnetic interference (EMI) susceptibility.
Operational amplifiers vary in susceptibility to radio frequency interference (RFI). RFI can generally be identified
as a variation in offset voltage or DC signal levels with changes in the interfering RF signal. The OPA333 is
specifically designed to minimize susceptibility to RFI and demonstrates remarkably low sensitivity compared to
previous generation devices. Strong RF fields may still cause varying offset levels.
10.1.2 DFN Layout Guidelines
Solder the exposed leadframe die pad on the DFN package to a thermal pad on the PCB. A mechanical drawing
showing an example layout is attached at the end of this data sheet. Refinements to this layout may be
necessary based on assembly process requirements. Mechanical drawings located at the end of this data sheet
list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are
intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push,
package shear, and similar board-level tests. Even with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
10.2 Layout Example
VIN
RG
+
RF
VOUT
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
RG
GND
VIN
RF
N/C
±IN
+IN
V±
N/C
V+
OUTPUT
N/C
VS+
GND
Use low-ESR, ceramic
bypass capacitor
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT
Figure 34. Layout Example
Ground (GND) plane on another layer
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: OPA333 OPA2333
Submit Documentation Feedback
23