LMH6552 Datasheet, PDF (23/38 Pages) Texas Instruments – 1.5-GHz Fully Differential Amplifier

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LMH6552
SNOSAX9I – APRIL 2007 – REVISED JANUARY 2015
275:
R_S = 50:
a ^VS
50:
V⁺
10:
V_CM
+
LMH6552
-
10:
V^-
1 PF _{2:1 (TURNS)}
-
V_O
50:
+
1 PF
275:
A_V = 9 V/V
Figure 48. Noise Figure Circuit Configuration
9.2.6 Driving Analog to Digital Converters
Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well, there are usually current spikes associated with
switched capacitor or sample and hold circuits. Figure 49 shows a combination circuit of the LMH6552 driving the
ADC12DL080. The two 125-Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and
ensure stability. In addition, the resistors, along with a 2.2-pF capacitor across the outputs (in parallel with the
ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched
capacitor input ADCs, the input capacitance will vary based on the clock cycle, as the ADC switches between the
sample and hold mode. See your particular ADC's datasheet for details.
50:
Single-Ended
AC-coupled
Source
61.8:
169:
49.9:
0.1 PF
169:
61.8:
357:
V⁺
-+
LMH6552
-
+
V^-
125:
ADC12DL080
12-Bit
80 MSPS
2.2 pF
C_IN
~ 7- 8 pF
125:
V_REF
357:
Figure 49. Driving a 12-bit ADC
Figure 50 shows the SFDR and SNR performance vs. frequency for the LMH6552 and ADC12DL080
combination circuit with the ADC input signal level at −1 dBFS. The ADC12DL080 is a dual 12-bit ADC with
maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to
differential mode. An external band-pass filter is inserted in series between the input signal source and the
amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input
impedance seen at the LMH6552 amplifier inputs, R_M is chosen to match Z_S || R_T for proper input balance.
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