DRV425 Datasheet, PDF (23/37 Pages) Texas Instruments – DRV425 Fluxgate Magnetic-Field Sensor

www.ti.com
DRV425
SBOS729 – OCTOBER 2015
Feature Description (continued)
Reference input REFIN is the common-mode voltage node for the output signal VOUT. Use the internal voltage
reference of the DRV425 by connecting the REFIN pin to the reference output REFOUT. To avoid mismatch
errors, use the same reference voltage for REFIN and the ADC. Alternatively, use an ADC with a pseudo-
differential input, with the positive input of the ADC connected to VOUT and the negative input connected to
REFIN of the DRV425.
7.3.3 Voltage Reference
The internal precision voltage reference circuit offers low-drift performance at the REFOUT output pin and is
used for internal biasing. The reference output is intended to be the common-mode voltage of the output (the
VOUT pin) to provide a bipolar signal swing. This low-impedance output tolerates sink and source currents of
±5 mA. However, fast load transients can generate ringing on this line. A small series resistor of a few ohms
improves the response, particularly for capacitive loads equal to or greater than 1 μF.
Adjust the value of the voltage reference output to the power supply of the DRV425 using mode selection pins
RSEL0 and RSEL1, as shown in Table 1.
MODE
V_REFOUT = 2.5 V
V_REFOUT = 1.65 V
Ratiometric output
RSEL1
0
0
1
Table 1. Reference Output Voltage Selection
RSEL0
0
1
x
DESCRIPTION
Use with a sensor module supply of 5 V
Use with a sensor module supply of 3.3 V
Provides an output centered on VDD / 2
In ratiometric output mode, an internal resistor divider divides the power-supply voltage by a factor of two.
7.3.4 Low-Power Operation of the DRV425
In applications with low-bandwidth or low sample-rate requirements, the average power dissipation of the
DRV425 can be significantly reduced by powering the device down between measurements. The DRV425
requires 300 μs to fully settle the analog output VOUT, as shown in Figure 66. To minimize power dissipation,
the device can be powered down immediately after acquiring the sample by the ADC.
VDD
VOUT
startup
Settling time:
300 µs
Figure 66. Settling Time of the DRV425 Output VOUT
7.4 Device Functional Modes
The DRV425 is operational when the power supply VDD is applied, as specified in the Specifications section.
The DRV425 has no additional functional modes.
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DRV425
Submit Documentation Feedback
23