DAC60096 Datasheet, PDF (23/51 Pages) Texas Instruments – 96-Channel, 12-Bit, Low-Power, Serial-Input, High-Voltage Output DAC

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DAC60096
SBAS721A – DECEMBER 2015 – REVISED JANUARY 2016
7.5 Programming
The DAC60096 is controlled through a flexible four-wire serial interface that is compatible with SPI type
interfaces used on many microcontrollers and DSP controllers. The interface provides read/write access to all
registers of the DAC60096.
For simplification of the register structure, communication to the device is done at a subsystem level through the
PTR global pointer register (address 0x6). Subsystem addressing is done through SID[1:0], where subsystem 1
is the default setting. Access to all other registers in the device will affect only the subsystem selected by SID.
The DAC pointer setting, DPTR[4:0], also in the PTR register allows access to the data registers (BUFA and
BUFB) for any of the DACs in the chosen subsystem.
Each serial interface access cycle is exactly 24 bits long. A frame is initiated by asserting the CS pin low. The
frame ends when the CS pin is deasserted high. The frame's first byte input to SDI is the instruction cycle which
identifies the request as a read or write, streaming or single, and the 4-bit address to be accessed. The following
bits in the frame form the data cycle. For all writes, data are clocked on the rising edge of SCLK. On read
access, data are clocked out on the SDO pin on either the falling edge or rising edge of SCLK according to the
PHAINV setting in each of the four subsystems CON registers (address 0x4, bits [7:6]).
Bit
Field
23
R/W
22
S
21:18
17:16
15:0
A[3:0]
Reserved
D[15:0]
Table 2. Serial Interface Cycle
Description
Identifies the communication as a read or write command to the addressed
register.
R/W = 0 sets a write operation. R/W = 1 sets a read operation.
Identifies the communication as a streaming operation.
S = 0 is used for single command instructions. Bit = 1 is used for streaming
operation.
Register address.
Specifies the register to be accessed during the read or write operation.
Reserved. Set to zeros for proper operation.
Data cycle bits.
If a write command, the data cycle bits are the values to be written to the
register with address A[3:0]
If a read command, the data cycle bits are don't care values.
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDI R/W S=0 A3 A2 A1 A0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
All Zeros
Figure 35. Serial Interface Write Bus Cycle
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDI
SDO
SDO
S=0 A3 A2 A1 A0
All Zeros
All Zeros
All Zeros
PHAINV = 01
D15 D14 D1A3ll DZe1r2osD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PHAINV = 10
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. Serial Interface Read Bus Cycle
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