BUF20800-Q1 Datasheet, PDF (23/32 Pages) Texas Instruments – 18-CHANNEL GAMMA VOLTAGE GENERATOR WITH TWO PROGRAMMABLE VCOM CHANNELS

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BUF20800-Q1
SBOS571 – AUGUST 2011
Figure 19. Evaluation Board
GENERAL PowerPad DESIGN CONSIDERATIONS
The BUF20800-Q1 is available in a thermally-enhanced PowerPAD package. This package is constructed using
a downset leadframe upon which the die is mounted, see Figure 20(a) and Figure 20(b). This arrangement
results in the lead frame being exposed as a thermal pad on the underside of the package; see Figure 20(c).
This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by
providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This provides the necessary thermal and mechanical connection between the
lead frame die pad and the PCB.
The PowerPAD must be connected to the most negative supply voltage on the device, GND_A and GND_D.
1. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal pad. Ideal thermal land size and thermal via patterns for
the HTSSOP-38 DCP package can be seen in the technical brief, PowerPAD Thermally-Enhanced Package
(SLMA002), available for download at www.ti.com. These holes should be 13 mils in diameter. Keep them
small, so that solder wicking through the holes is not a problem during reflow. An example thermal land
pattern mechanical drawing is attached to the end of this data sheet.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the BUF20800-Q1 IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered; thus, wicking is not a problem.
4. Connect all holes to the internal plane that is at the same voltage potential as the GND pins.
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): BUF20800-Q1
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