ADS58C28_14 Datasheet, PDF (23/68 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
www.ti.com
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RESET
READOUT
Bits[7:2]
Bit 1
Bit 0
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic
levels running from the DRVDD supply. See the Serial Register Readout section.
7
Bits[7:2]
Bits[1:0]
Register Address 01h (Default = 00h)
6
5
4
3
2
1
0
LVDS SWING
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing increases to ±200mV
001111 = LVDS swing increases to ±125mV
Always write '0'
7
0
Bits[7:2]
Bits[1:0]
Register Address 03h (Default = 00h)
6
5
4
3
2
1
0
0
0
0
0
0
HIGH PERF MODE
Always write '0'
HIGH PERF MODE: High-performance mode
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS58C28
Submit Documentation Feedback
23