ADS58C28_14 Datasheet, PDF (19/68 Pages) Texas Instruments – Dual Channel IF Receiver with SNRBoost3G

ADS58C28
www.ti.com
SBAS509B – JUNE 2010 – REVISED OCTOBER 2010
DETAILS OF SERIAL INTERFACE
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of
16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining
eight bits are the register data. The interface can work with SCLK frequencies from 20MHz down to very low
speeds (of a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on the RESET pin (of width greater than 10ns), as
shown in Figure 9; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
SDATA
SCLK
SEN
Register Address
Register Data
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t_DH
t_SCLK
t_DSU
t_SLOADS
t_SLOADH
RESET
Figure 9. Serial Interface Timing
Table 9. Serial Interface Timing Characteristics⁽¹⁾
f_SCLK
t_SLOADS
t_SLOADH
t_DSU
t_DH
PARAMETER
SCLK frequency (equal to 1/t_SCLK)
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
SDATA hold time
MIN
TYP
MAX
UNIT
> DC
20
MHz
25
ns
25
ns
25
ns
25
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC.
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on pin 64.
Copyright © 2010, Texas Instruments Incorporated
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