TLC2932_15 Datasheet, PDF (22/29 Pages) Texas Instruments – HIGH-PERFORMANCE PHASE-LOCKED LOOP

TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
REF IN
DGND
VDD
1
LOGIC VDD (Digital)
2 SELECT
3 _{VCO OUT}
4 FIN – A
5 FIN – B
VCO
14
VCO VDD
1/2 fosc
13
BIAS
12
VCO IN
11
VCO GND
VCO INHIBIT 10
6 ^{PFD OUT}
Phase
Comparator
7
LOGIC GND (Digital)
PFD INHIBIT ₉
8
NC
Divide
By
N
DGND
AVDD
R1†
0.22 µF
R3
C2
R2
C1
AGND
S3
S4
S5
† _{RBIAS resistor}
R4 R5
R6
DVDD
Figure 28. Evaluation and Operation Schematic
DGND
PCB layout considerations
The TLC2932 contains a high frequency analog oscillator; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2932 user:
D External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D LOGIC V_DD and VCO V_DD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D VCO V_DD to GND and LOGIC V_DD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
D The no-connection (NC) terminal on the package should be connected to GND.
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