TIOS101 Datasheet, PDF (22/26 Pages) Texas Instruments – Digital Sensor Output Drivers with Integrated Surge Protection

TIOS101
SLLSEV6 – JULY 2017
11 Layout
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11.1 Layout Guidelines
• Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as GND, layer 3 for the 24-V supply plane (VCC), and layer 4 for the regulated output supply
(VCC_IN/OUT).
• Connect the thermal pad to GND with maximum amount of thermal vias for best thermal performance.
• Use entire planes for VCC, VCC_IN/OUT and GND to assure minimum inductance.
• The VCC terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor with a
minimum value of 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on
max sensor supply fault rating) and an X5R or X7R dielectric.
• • The optimum placement of the capacitor is closest to the VCC and GND terminals to reduce supply drops
during large supply current loads. See Figure 26 for a PCB layout example.
• Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
• Connect the R_SET resistor between ILIM_ADJ and GND.
• Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, 1 μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (VCC)
VIA to Layer 3: 24V Supply Plane (GND)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
1uF/10V
NFAULT
VCC_IN/OUT
NC
IN
EN
NC
VCC
OUT
GND
100nF/
50V
Exposed Thermal
Pad Area
R_SET
Use Multiple Vias for
VCC and GND
Figure 26. Layout Example
VCC
OUT
GND
22
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