OPA2810 Datasheet, PDF (22/26 Pages) Texas Instruments – OPA2810 Dual High-Performance, Low-Power, Wide Supply Range, Rail-to-Rail Input/Output FET-Input Operational Amplifier

OPA2810
SBOS789 – AUGUST 2017
www.ti.com
Layout Guidelines (continued)
5. Socketing a high speed part like the OPA2810 is not recommended. The additional lead length and pin-
to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA2810 onto the board.
10.2 Layout Example
VS+
Representative schematic of a
single channel
CBYP
+
RS
±
CBYP
VS-
RG
RF
Place series output resistors
RS
close to output pin to minimize
1
parasitic capacitance
RF
2
RG
3
Place bypass capacitors
close to power pins
4
CBYP
CBYP
8
RS
7
RF
6
RG
5
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitors
close to power pins
Place gain and feedback resistors
close to pins to minimize stray
capacitance
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
Figure 7. Layout Recommendation
10.3 Thermal Considerations
The OPA2810 does not require heat sinking or airflow in most applications. Maximum allowed junction
temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction
temperature to exceed 150°C.
Operating junction temperature (T_J) is given by T_A + P_D × θ_JA. The total internal power dissipation (P_D) is the sum
of quiescent power (P_DQ) and additional power dissipated in the output stage (P_DL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. P_DL
depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when
the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this
condition P_DL = V_S ²/(4 × R_L) where R_L includes feedback network loading.
Note that it is the power in the output stage and not into the load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using an OPA2810-DGK (VSSOP package) configured as a
unity gain buffer, operating on ±12V supplies at an ambient temperature of +25°C and driving a grounded 200-Ω
load.
P_D = 24 V × 7.2 mA + 12² /(4 × 200 Ω) = 353 mW
Maximum T_J = 25°C + (0.353 W × 171°C/W) = 85.4°C.
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