OPA2810 Datasheet, PDF (21/26 Pages) Texas Instruments – OPA2810 Dual High-Performance, Low-Power, Wide Supply Range, Rail-to-Rail Input/Output FET-Input Operational Amplifier

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10 Layout
OPA2810
SBOS789 – AUGUST 2017
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA2810 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability—on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, open a window around the
signal I/O pins in all of the ground and power planes around those pins. Otherwise, ground and power planes
must be unbroken elsewhere on the board.
2. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors.
At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF
to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These
can be placed somewhat farther from the device and shared among several devices in the same area of the
PC board.
3. Careful selection and placement of external components preserve the high frequency performance of
the OPA2810. Resistors must be a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high
frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use
wirewound type resistors in a high frequency application. Because the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as
close as possible to the output pin. Other network components, such as noninverting input termination
resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the
external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal film or surface mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 10 kΩ, this parasitic capacitance can add a pole or zero close to the
OPA2810s GBP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. Lowering the resistor values keep the resistor noise
terms low, and minimize the effect of its parasitic capacitance, however lower resistor values increase the
dynamic power consumption because R_F and R_G become part of the amplifiers output load network.
Transimpedance applications (see ) can use whatever feedback resistor is required by the application as
long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the
inverting node.
4. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground
and power planes opened up around them. Estimate the total capacitive load and set R_S from the plot of
Recommended R_S vs Capacitive Load. Low parasitic capacitive loads (< 35 pF) may not need an R_S
because the OPA2810 is nominally compensated to operate with a 35-pF parasitic load. Higher parasitic
capacitive loads without an R_S are allowed as the signal gain increases (increasing the unloaded phase
margin) If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is
normally not necessary onboard, and a higher impedance environment improves distortion. With a
characteristic board trace impedance defined based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA2810 is used as well as a terminating shunt resistor
at the input of the destination device. Remember also that the terminating impedance is the parallel
combination of the shunt resistor and the input impedance of the destination device— this total effective
impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series resistor value as shown in the plot of
Recommended R_S vs Capacitive Load. This does not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low, the signal attenuates because of the voltage
divider formed by the series output into the terminating impedance.
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