OPA2677IDDA Datasheet, PDF (22/38 Pages) Texas Instruments – Dual, Wideband, High Output Current Operational Amplifier

As a reminder, the differential gain is expressed as:
G_D
= 1+
2 • R_F
R_G
(19)
The output noise can be expressed as shown below:
(20)
( ) E_O =
2
•
G_D2
•


e_N2
+
i_N • R_S
2
+
4kTR_S


+ 2(i_IR_F )²
+ 2(4kTR_FG_D )
Dividing this expression by the differential noise gain
(G_D = (1 + 2R_F/R_G)) gives the equivalent input referred
spot noise voltage at the noninverting input, as shown in
Equation 21.
(21)
( ) E_O =
2
•


e_N2
+
i_N • R_S
2
+
4kTR_S


+

2_
i_IR_F
G_D
²

+

2_
4kTR_F
G_D


Evaluating these equations for the OPA2677 ADSL circuit
and component values of Figure 6 gives a total output spot
noise voltage of 31.8nV/√Hz and a total equivalent input spot
noise voltage of 3.6nV/√Hz.
In order to minimize the output noise due to the noninverting
input bias current noise, it is recommended to keep the
noninverting source impedance as low as possible.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp such as the OPA2677 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteris-
tics show an input offset voltage comparable to high-speed,
voltage-feedback amplifiers; however, the two input bias
currents are somewhat higher and are unmatched. While
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally re-
duce the output DC offset for wideband current-feedback op
amps. Because the two input bias currents are unrelated in
both magnitude and polarity, matching the input source
impedance to reduce error contribution to the output is
ineffective. Evaluating the configuration of Figure 1, using
worst-case +25°C input offset voltage and the two input bias
currents, gives a worst-case output offset range equal to:
V_OFF = ± (NG • V_OS(MAX)) + (I_BN • R_S/2 • NG) ± (I_BI • R_F)
where NG = noninverting signal gain
= ± (4 • 4.5mV) + (30µA • 25Ω • 4) ± (402Ω • 30µA)
= ±18mV + 3mV ± 12.06mV
V_OFF = –29.06mV to +35.06mV
THERMAL ANALYSIS
Due to the high output power capability of the OPA2677, heat-
sinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
sets the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction tem-
perature be allowed to exceed 175°C. Operating junction
temperature (T_J) is given by T_A + P_D • θ_JA. The total internal
power dissipation (P_D) is the sum of quiescent power (P_DQ) and
additional power dissipation in the output stage (P_DL) to deliver
load power. Quiescent power is the specified no-load supply
current times the total supply voltage across the part. P_DL
depends on the required output signal and load, but for a
grounded resistive load, P_DL is at a maximum when the output
is fixed at a voltage equal to 1/2 of either supply voltage (for
equal bipolar supplies). Under this condition, P_DL = V_S2 /(4 • R_L)
where R_L includes feedback network loading. Note that it is the
power in the output stage and not into the load that determines
internal power dissipation. As a worst-case example, compute
the maximum T_J using an OPA2677 SO-8 in the circuit of
Figure 1 operating at the maximum specified ambient tempera-
ture of +85°C with both outputs driving a grounded 20Ω load to
+2.5V.
P_D = 12V • 18mA + 2 • [6² / (4 • (20Ω || 534Ω))] = 882mW
Maximum T_J = +85°C + (0.83 • 125°C/W) = 170°C
This absolute worst-case condition exceeds specified maxi-
mum junction temperature. This extreme case is not normally
encountered. Where high internal power dissipation is antici-
pated, consider the thermal slug package version.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency am-
plifier like the OPA2677 requires careful attention to board
layout parasitic and external component types. Recommen-
dations that optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability; on the noninverting
input, it can react with the source impedance to cause
unintentional band limiting. To reduce unwanted capaci-
tance, a window around the signal I/O pins should be opened
in all of the ground and power planes around those pins.
Otherwise, ground and power planes should be unbroken
elsewhere on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capaci-
tor across the two power supplies (for bipolar operation)
improves 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These can be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PCB.
c) Careful selection and placement of external compo-
nents preserve the high-frequency performance of the
OPA2677. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall
layout. Metal film and carbon composition axially leaded
resistors can also provide good high-frequency performance.
22
OPA2677
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