LP3971_16 Datasheet, PDF (22/52 Pages) Texas Instruments – Power Management Unit for Advanced Application Processors

LP3971
SNVS432V – JANUARY 2006 – REVISED MAY 2013
Write Cycle
Figure 20. Write cycle
start msb Chip Address lsb w ack Msb Register Add lsb ack msb DATA lsb
ack stop
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SCL
SDA
start
Id = 34h
w ack
addr = 02h
ack
DGGUHVV K¶02 data
ack stop
Read Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function as follows.
Figure 21. Read Cycle
start msb Chip Address lsb w ack msb Register Add lsb ack rs msb Chip Address lsb r ack msb DATA lsb ack stop
SCL
SDA
start
Id = 34h
w ack
addr = 00h
ack rs
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 34h (Chip Address)
Id = 34h
r ack $GGUHVV K¶00 data ack stop
Figure 22. I²C DVM Timing for V_CC_APPS (Buck1)
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
S
START
condition
1
I²C - bus.
acknowledge
8
9
clock pulse for
acknowledgement
9ROWDJH µµ%¶¶
V_CC_APPS
9ROWDJH µµ$¶¶
5 Ps TYP
LP3971 I²C Register Definitions
I²C CONTROL REGISTERS
Register
Address
8h'02
8h'07
Register
Name
ISR
SCR1
Read/
Write
R
R/W
Interrupt Status Register A
System Control Register 1
Register Description
22
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