LMK00304 Datasheet, PDF (22/25 Pages) Texas Instruments – 3-GHz 4-Output Differential Clock Buffer/Level Translator

dBc at 312.5 MHz. Using Equation 12, these phase spur lev-
els translate to Deterministic Jitter values of 2.57 ps pk-pk at
156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has
shown that the PSRR performance of the device improves for
Vcco = 3.3 V under the same ripple amplitude and frequency
conditions.
14.4.3 Thermal Management
Power dissipation in the LMK00304 device can be high
enough to require attention to thermal management. For re-
liability and performance reasons the die temperature should
be limited to a maximum of 125 °C. That is, as an estimate,
T_A (ambient temperature) plus device power dissipation times
θ_JA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to the printed circuit board. To maximize the re-
moval of heat from the package a thermal land pattern in-
cluding multiple vias to a ground plane must be incorporated
on the PCB within the footprint of the package. The exposed
pad must be soldered down to ensure adequate heat con-
duction out of the package.
A recommended land and via pattern is shown in Figure 17.
More information on soldering LLP packages can be obtained
at: http://www.national.com/analog/packaging/.
A recommended footprint including recommended solder
mask and solder paste layers can be found at: http://
www.national.com/analog/packaging/gerber for the SQA32A
package.
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 17 should connect these top and bottom
copper layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
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FIGURE 17. Recommended Land and Via Pattern
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