LMK00304 Datasheet, PDF (21/25 Pages) Texas Instruments – 3-GHz 4-Output Differential Clock Buffer/Level Translator

14.4.1.1 Power Dissipation Example: Worst-Case Dissipation
This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this
case, the maximum supply voltage and supply current values specified in Section 11.0 Electrical Characteristics are used.
• Max V_CC = V_CCO = 3.465 V. Max I_CC and I_CCO values.
• CLKin0/CLKin0* input is selected.
• Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to V_T = Vcco - 2 V.
• REFout is enabled with 5 pF load.
• T_A = 85 °C
Using the power calculations from the previous section and maximum supply current specifications, we can compute P_TOTAL and
P_DEVICE.
• From Equation 5: I_{CC_TOTAL} = 10.5 mA + 48 mA + 5.5 mA = 64 mA
• From I_{CCO_PECL} max spec: I_{CCO_BANK} = 50% of I_{CCO_PECL} = 81.5 mA
• From Equation 7: P_TOTAL = (3.465 V * 64 mA) + (3.465 V * 81.5 mA)+ (3.465 V * 81.5 mA) + (3.465 V * 10 mA) = 821 mW
• From Equation 8: P_{RT_PECL} = ((2.57 V - 1.47 V)²/50 Ω) + ((1.72 V - 1.47 V)²/50 Ω) = 25.5 mW (per output pair)
• From Equation 9: P_{VTT_PECL} = 1.47 V * [ ((2.57 V - 1.47 V) / 50 Ω) + ((1.72 V - 1.47 V) / 50 Ω) ] = 39.5 mW (per output pair)
• From Equation 10: P_{RT_HCSL} = 0 mW (no HCSL outputs)
• From Equation 11: P_DEVICE = 821 mW - (4 * (25.5 mW + 39.5 mW)) - 0 mW = 561 mW
In this worst-case example, the IC device will dissipate about 561 mW or 68% of the total power (821 mW), while the remaining
32% will be dissipated in the emitter resistors (102 mW for 4 pairs) and termination voltage (158 mW into Vcco - 2 V). Based on
θ_JA of 38.1 °C/W, the estimate die junction temperature would be about 21.4 °C above ambient, or 106.4 °C when T_A = 85 °C.
14.4.2 Power Supply Bypassing
The Vcc and Vcco power supplies should have a high-fre-
quency bypass capacitor, such as 0.1 uF or 0.01 uF, placed
very close to each supply pin. 1 uF to 10 uF decoupling ca-
pacitors should also be placed nearby the device between the
supply and ground planes. All bypass and decoupling capac-
itors should have short connections to the supply and ground
plane through a short trace or via to minimize series induc-
tance.
14.4.2.1 Power Supply Ripple Rejection
In practical system applications, power supply noise (ripple)
can be generated from switching power supplies, digital
ASICs or FPGAs, etc. While power supply bypassing will help
filter out some of this noise, it is important to understand the
effect of power supply ripple on the device performance.
When a single-tone sinusoidal signal is applied to the power
supply of a clock distribution device, such as LMK00304, it
can produce narrow-band phase modulation as well as am-
plitude modulation on the clock output (carrier). In the single-
side band phase noise spectrum, the ripple-induced phase
modulation appears as a phase spur level relative to the car-
rier (measured in dBc).
For the LMK00304, power supply ripple rejection, or PSRR,
was measured as the single-sideband phase spur level (in
dBc) modulated onto the clock output when a ripple signal
was injected onto the Vcco supply. The PSRR test setup is
shown in Figure 16.
FIGURE 16. PSRR Test Setup
30177340
A signal generator was used to inject a sinusoidal signal onto
the Vcco supply of the DUT board, and the peak-to-peak rip-
ple amplitude was measured at the Vcco pins of the device.
A limiting amplifier was used to remove amplitude modulation
on the differential output clock and convert it to a single-ended
signal for the phase noise analyzer. The phase spur level
measurements were taken for clock frequencies of 156.25
MHz and 312.5 MHz under the following power supply ripple
conditions:
• Ripple amplitude: 100 mVpp on Vcco = 2.5 V
• Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz
Assuming no amplitude modulation effects and small index
modulation, the peak-to-peak deterministic jitter (DJ) can be
calculated using the measured single-sideband phase spur
level (PSRR) as follows:
DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹²
(12)
The “PSRR vs. Ripple Frequency” plots in Section 13.0 Typ-
ical Performance Characteristics show the ripple-induced
phase spur levels for the differential output types at 156.25
MHz and 312.5 MHz . The LMK00304 exhibits very good and
well-behaved PSRR characteristics across the ripple frequen-
cy range for all differential output types. The phase spur levels
for LVPECL are below -64 dBc at 156.25 MHz and below -62
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