DM3730_12 Datasheet, PDF (218/280 Pages) Texas Instruments – DM3730, DM3725 Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
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(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
(2) See Section 4.3.4, Processor Clocks.
Table 6-60. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics—Falling Edge and Receive
Mode^{(1) (2)}
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
B2 t_d(CLKAE-FSV) Delay time, mcbsp1_clkr / mcbspx_clkx active edge to
0.7
14.79
0.7
29.58
ns
mcbsp1_fsr / mcbspx_fsx valid
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
(2) See Section 4.3.4, Processor Clocks.
Table 6-61. McBSP4 (Set #1) Timing Requirements—Falling Edge and Receive Mode^{(1) (2)}
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
B3
t_{su(DRV-CLKXAE)} Setup time, mcbspx_dr valid before
Master
2.87
8.63
ns
mcbspx_clkx active edge
Slave
3.67
7.94
ns
B4
t_{h(CLKXAE-DRV)} Hold time, mcbspx_dr valid after
Master
1.01
1.01
ns
mcbspx_clkx active edge
Slave
0.4
0.4
ns
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before mcbspx_clkx
3.67
7.94
ns
active edge
B6 t_{h(CLKXAE-FSXV)} Hold time, mcbspx_fsx valid after mcbspx_clkx active
0.5
0.5
ns
edge
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-63 and Table 6-64.
(2) See Section 4.3.4, Processor Clocks.
Table 6-62. McBSP4 (Set #1) Switching Characteristics—Falling Edge and Receive Mode^{(1) (2)}
NO.
PARAMETER
OPP100
OPP50
UNIT
MIN
MAX
MIN
MAX
B2 t_{d(CLKXAE-FSXV)} Delay time, mcbspx_clkx active edge to mcbspx_fsx
0.7
16.56
0.7
33.12
ns
valid
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-63 and Table 6-64.
(2) See Section 4.3.4, Processor Clocks.
Table 6-63. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements—Falling Edge and Receive Mode^{(1) (2)}
NO.
PARAMETER
B3
t_{su(DRV-CLKXAE)} Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
B4
t_{h(CLKXAE-DRV)} Hold time, mcbspx_dr valid after
mcbspx_clkx active edge
Master
Slave
B5 t_{su(FSXV-CLKXAE)} Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
B6 t_{h(CLKXAE-FSXV)} Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
OPP100
MIN
MAX
6.5
5.81
1.01
0.4
5.81
0.5
OPP50
MIN
MAX
12.9
12.21
1.01
0.4
12.21
0.5
UNIT
ns
ns
ns
ns
ns
ns
218 Timing Requirements and Switching Characteristics
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