DM3730_12 Datasheet, PDF (160/280 Pages) Texas Instruments – DM3730, DM3725 Digital Media Processors

DM3730, DM3725
SPRS685D – AUGUST 2010 – REVISED JULY 2011
6.4 External Memory Interfaces
The device includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• SDRAM controller (SDRC)
6.4.1 General-Purpose Memory Controller (GPMC)
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NOTE
For more information, see Memory Subsystem / General-Purpose Memory Controller section
of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
The GPMC is the unified memory controller used to interface external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
6.4.1.1 GPMC/NOR Flash—Synchronous Mode
Table 6-3 and Table 6-4 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 6-2 through Figure 6-6).
Table 6-2. GPMC/NOR Flash Timing Conditions—Synchronous Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
Output Conditions
C_LOAD
Output load capacitance⁽¹⁾
(1) The load setting of the IO buffer: LB0 = 1.
VALUE
1.8
1.8
12
UNIT
ns
ns
pF
Table 6-3. GPMC/NOR Flash Timing Requirements—Synchronous Mode⁽¹⁾
NO.
PARAMETER
F12
t_su(dV-clkH)
Setup time, input data gpmc_d[15:0] valid before
output clock gpmc_clk high
F13
F21
F22
t_h(clkH-dV)
t_{su(waitV-clkH)}
t_{h(clkH-waitV)}
Hold time, input data gpmc_d[15:0] valid after output
clock gpmc_clk high
Setup time, input wait gpmc_waitx⁽²⁾ valid before
output clock gpmc_clk high
Hold time, input wait gpmc_waitx⁽²⁾ valid after output
clock gpmc_clk high
(1) See Section 4.3.4, Processor Clocks.
(2) In gpmc_waitx, x is equal to 0, 1, 2, or 3.
OPP100
MIN
MAX
2.3
1.5
2.3
1.9
OPP50
MIN
MAX
2.3
1.5
2.3
1.9
UNIT
ns
ns
ns
ns
Table 6-4. GPMC/NOR Flash Switching Characteristics—Synchronous Mode^{(2) (18)}
NO.
F0
1 / t_c(clk)
F1
t_w(clkH)
F1
t_w(clkL)
PARAMETER
Frequency⁽¹⁵⁾, output clock gpmc_clk
Typical pulse duration, output clock gpmc_clk high
Typical pulse duration, output clock gpmc_clk low
OPP100
MIN
MAX
100
0.5P⁽¹²⁾
0.5P⁽¹²⁾
OPP50
MIN
MAX
100
0.5P⁽¹²⁾
0.5P⁽¹²⁾
UNIT
MHz
ns
ns
160 Timing Requirements and Switching Characteristics
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