DM3730_12 Datasheet, PDF (1/280 Pages) Texas Instruments – DM3730, DM3725 Digital Media Processors

DM3730, DM3725
www.ti.com
SPRS685D – AUGUST 2010 – REVISED JULY 2011
DM3730, DM3725
Digital Media Processors
Check for Samples: DM3730, DM3725
1 DM3730, DM3725 Digital Media Processors
1.1 Features
123456
• DM3730/25 Digital Media Processors:
– Compatible with OMAP™ 3 Architecture
– ARM^® Microprocessor (MPU) Subsystem
• Up to 1-GHz ARM^® Cortex™-A8 Core
Also supports 300, 600, and 800-MHz
operation
• NEON™ SIMD Coprocessor
– High Performance Image, Video, Audio
(IVA2.2^TM) Accelerator Subsystem
• Up to 800-MHz TMS320C64x+^TM DSP Core
Also supports 260, 520, and 660-MHz
operation
• Enhanced Direct Memory Access (EDMA)
Controller (128 Independent Channels)
• Video Hardware Accelerators
– POWERVR SGX™ Graphics Accelerator
(DM3730 only)
• Tile Based Architecture Delivering up to
20 MPoly/sec
• Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality
• Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
• Fine Grained Task Switching, Load
Balancing, and Power Management
• Programmable High Quality Image
Anti-Aliasing
– Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x+^TM DSP Core
• Eight Highly Independent Functional
Units
• Six ALUs (32-/40-Bit); Each Supports
Single 32- bit, Dual 16-bit, or Quad 8-bit,
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
• Load-Store Architecture With
Non-Aligned Support
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
• All Instructions Conditional
• Additional C64x+^TM Enhancements
– Protected Mode Operation
– Expectations Support for Error
Detection and Program Redirection
– Hardware Support for Modulo Loop
Operation
– C64x+^TM L1/L2 Memory Architecture
• 32K-Byte L1P Program RAM/Cache
(Direct Mapped)
• 80K-Byte L1D Data RAM/Cache (2-Way
Set- Associative)
• 64K-Byte L2 Unified Mapped RAM/Cache
(4- Way Set-Associative)
• 32K-Byte L2 Shared SRAM and 16K-Byte
L2 ROM
– C64x+^TM Instruction Set Features
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions
• Additional Instructions to Support
Complex Multiplies
– External Memory Interfaces:
• SDRAM Controller (SDRC)
– 16, 32-bit Memory Controller With
1G-Byte Total Address Space
– Interfaces to Low-Power SDRAM
– SDRAM Memory Scheduler (SMS) and
Rotation Engine
• General Purpose Memory Controller
(GPMC)
– 16-bit Wide Multiplexed Address/Data
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
POWERVR SGX is a trademark of Imagination Technologies Ltd.
2
OMAP is a trademark of Texas Instruments.
3
Cortex, NEON are trademarks of ARM Limited.
4
ARM is a registered trademark of ARM Ltd.
5
All other trademarks are the property of their respective owners.
6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated