AM5K2E04_16 Datasheet, PDF (214/252 Pages) Texas Instruments – AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)

AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
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10.7 NETCP PLL
The NETCP PLL generates interface clocks for the Network Coprocessor. Using the NETCPCLKSEL pin
the user can select the input source of the NETCP PLL as either the output of the Core PLL mux or the
NETCPCLK clock reference source. When coming out of power-on reset, NETCP PLL comes out in a
bypass mode and needs to be programmed to a valid frequency before being enabled and used.
NETCP PLL power is supplied via the NETCP PLL power-supply pin (AVDDA3). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices
application report (SPRABV0) for detailed recommendations.
CORECLK(P|N)
NETCPCLK(P|N)
NETCPCLKSEL
NETCP
Clock Source
PLLM
NETCP PLL
MUX
SYSCLK0
CLKOD
PLLD
0
VCO
0
1
1
/3
0
NETCP
Sub-system
1
BYPASS
NETCPPLLCTL1.PAPLL
(bit13)
Figure 10-26. NETCP PLL Block Diagram
10.7.1 NETCP PLL Local Clock Dividers
The clock signal from the NETCP PLL Controller is routed to the Network Coprocessor. The NETCP
module has two internal dividers with fixed division ratios. See table Table 10-31.
10.7.2 NETCP PLL Control Registers
The NETCP PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. NETCP
PLL can be controlled using the NETCPPLLCTL0 and NETCPPLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these
registers, software must go through an unlocking sequence using the KICK0 and KICK1 registers. For
suggested configuration values, see Section 8.1.4. See Section 8.2.3.4 for the address location of the
registers and locking and unlocking sequences for accessing these registers. These registers are reset on
POR only.
Figure 10-27. NETCP PLL Control Register 0 (NETCPPLLCTL0)
31
24
23
22
19
18
6
BWADJ[7:0]
BYPASS
CLKOD
PLLM
RW,+0000 1001
RW,+0
RW,+0001
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
5
0
PLLD
RW,+000000
Table 10-31. NETCP PLL Control Register 0 Field Descriptions (NETCPPLLCTL0)
Bit Field
31-24 BWADJ[7:0]
23
BYPASS
22-19 CLKOD
Description
BWADJ[11:8] and BWADJ[7:0] are located in NETCPPLLCTL0 and NETCPPLLCTL1 registers. BWADJ[11:0]
should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ =
((PLLM+1)>>1) - 1.
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
A 4-bit field that selects the values for the PLL post divider. Valid post divider values are 1 and even values
from 2 to 16. CLKOD field is loaded with output divide value minus 1
214 AM5K2E0x Peripheral Information and Electrical Specifications
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