AM5K2E04_16 Datasheet, PDF (132/252 Pages) Texas Instruments – AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)

AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
www.ti.com
Figure 8-2. Sleep Boot Mode Configuration Fields Description
DEVSTAT Boot Mode Pins ROM Mapping
16 15 14 13
12 11 10 9
8
7
6
5
4
3
2
1
0
X
X
0
X PLLEN
X
Boot
Master
Sys PLL Config
Min
000
Lendian
Bit
16-15
14
Field
Reserved
Boot Devices
13
Reserved
12
PLLEN
11-9
8
7-5
4
Reserved
Boot Master
SYS PLL
Setting
Min
3-1 Boot Devices
0
Lendian
Table 8-3. Sleep Boot Configuration Field Descriptions
Description
Reserved
Boot Device- used in conjunction with Boot Devices [Used in conjunction with bits 3-1]
• 0 = Sleep (default)
• Others = Other boot modes
Enable the System PLL
• 0 = PLL disabled (default)
• 1 = PLL enabled
Reserved
This pin must be pulled down to GND
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for
the device. Table 8-24 shows settings for various input clock frequencies.
Minimum boot configuration select bit.
• 0 = Minimum boot pin select disabled
• 1 = Minimum boot pin select enabled.
When Min = 1, a predetermined set of values is configured (see the Device Configuration Field Descriptions table
for configuration bits with a "(default)" tag added in the description column).
When Min = 0, all fields must be independently configured.
Boot Devices[3:1] used in conjunction with Boot Device [14]
• 000 = Sleep
• Others = Other boot modes
Endianess (device)
• 0 = Big endian
• 1 = Little endian
8.1.2.2.2 I²C Boot Device Configuration
8.1.2.2.2.1 I²C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified
address.
16 15 14
Slave Addr 1
Figure 8-3. I²C Passive Mode Device Configuration Fields
13 12 11
Port
DEVSTAT Boot Mode Pins ROM Mapping
10
9
8
7
6
5
4
X
Boot
Master
Sys PLL Config
Min
3
2
1
000
0
Lendian
Bit Field
16-15 Slave Addr
Table 8-4. I²C Passive Mode Device Configuration Field Descriptions
Description
I²C Slave boot bus address
• 0 = I²C slave boot bus address is 0x00
• 1 = I²C slave boot bus address is 0x10 (default)
• 2 = I²C slave boot bus address is 0x20
• 3 = I²C slave boot bus address is 0x30
132 Device Boot and Configuration
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