AM5K2E04_16 Datasheet, PDF (1/252 Pages) Texas Instruments – AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)

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AM5K2E04, AM5K2E02
SPRS864D – NOVEMBER 2012 – REVISED MARCH 2015
AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
1 AM5K2E0x Features and Description
1.1 Features
1
• ARM^® Cortex^®-A15 MPCore™ CorePac
– Up to Four ARM Cortex-A15 Processor Cores at
up to 1.4-GHz
– 4MB L2 Cache Memory Shared by all Cortex-
A15 Processor Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE)
Master Port, Connected to MSMC (Multicore
Shared Memory Controller) for Low Latency
Access to SRAM and DDR3
• Multicore Shared Memory Controller (MSMC)
– 2 MB SRAM Memory for ARM CorePac
– Memory Protection Unit for Both SRAM and
DDR3_EMIF
• Multicore Navigator
– 8k Multi-Purpose Hardware Queues with Queue
Manager
– One Packet-Based DMA Engine for Zero-
Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
• Transport Plane IPsec, GTP-U, SCTP,
PDCP
• L2 User Plane PDCP (RoHC, Air Ciphering)
• 1 Gbps Wire Speed Throughput at 1.5
MPackets Per Second
– Security Accelerator Engine Enables Support for
• IPSec, SRTP, 3GPP and WiMAX Air
Interface, and SSL/TLS Security
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
Hash), MD5
• Up to 6.4 Gbps IPSec and 3 Gbps Air
Ciphering
– Ethernet Subsystem
• Eight SGMII Ports with Wire Rate Switching
• IEEE1588 v2 (with Annex D/E/F) Support
• 8 Gbps Total Ingress/Egress Ethernet BW
from Core
• Audio/Video Bridging (802.1Qav/D6.0)
• QOS Capability
• DSCP Priority Mapping
• Peripherals
– Two PCIe Gen2 Controllers with Support for
• Two Lanes per Controller
• Supports Up to 5 GBaud
– One HyperLink
• Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
• Supports Up to 50 GBaud
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
• Two SGMII/XFI Ports with Wire Rate
Switching and MACSEC Support
• IEEE1588 v2 (with Annex D/E/F) Support
– One 72-Bit DDR3/DDR3L Interface with Speeds
Up to 1600 MTPS in DDR3 Mode
– EMIF16 Interface
– Two USB 2.0/3.0 Controllers
– USIM Interface
– Two UART Interfaces
– Three I²C Interfaces
– 32 GPIO Pins
– Three SPI Interfaces
– One TSIP
• Support 1024 DS0s
• Support 2 Lanes at 32.768/16.3848.192
Mbps Per Lane
• System Resources
– Three On-Chip PLLs
– SmartReflex Automatic Voltage Scaling
– Semaphore Module
– Twelve 64-Bit Timers
– Five Enhanced Direct Memory Access (EDMA)
Modules
• Commercial Case Temperature:
– 0ºC to 85ºC
• Extended Case Temperature:
– -40ºC to 100ºC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.