AM3517_16 Datasheet, PDF (213/223 Pages) Texas Instruments – AM3517, AM3505 Sitara™ Processors

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AM3517, AM3505
SPRS550F – OCTOBER 2009 – REVISED JULY 2014
jtag_tck
jtag_rtck
jtag_tdi
jtag_tms
jtag_emux(IN)
jtag_tdo
jtag_emux(OUT)
JT4
JT5
JT6
JT1
JT2
JT3
JT7
JT8
JT9
JT10
JT12
JT13
JT11
JT14
In jtag_emux, x is equal to 0 to 1.
Figure 6-73. JTAG Interface Timing Free Running Clock Mode
030-113
6.8.2.2 JTAG Adaptive Clock Mode
Table 6-158 through Table 6-160 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 6-158. JTAG Timing Conditions Adaptive Clock Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
C_LOAD
Input signal rise time
Input signal fall time
Output load capacitance
1.8 V
MAX
5
5
3.3 V
MAX
3
3
30
UNIT
ns
ns
pF
Table 6-159. JTAG Timing Requirements Adaptive Clock Mode⁽¹⁾⁽²⁾
NO.
PARAMETER
1.8 V
MIN
MAX
3.3 V
MIN
MAX
JA4
t_c(tck)
Cycle time
20
JA5
t_w(tckL)
Typical pulse duration, jtag_tck low
10
JA6
t_w(tckH)
Typical pulse duration, jtag_tck high
10
t_dc(lclk)
Duty cycle error, jtag_tck
-2500
2500
t_j(lclk)
Cycle jitter
-1500
1500
JA7
t_{su(tdiV-tckH)}
Setup time, jtag_tdi valid before jtag_tck high
13.8
JA8
t_h(tdiV-tckH)
Hold time, jtag_tdi valid after jtag_tck high
13.8
JA9
t_{su(tmsV-tckH)}
Setup time, jtag_tms valid before jtag_tck high
13.8
JA10 t_h(tmsV-tckH)
Hold time, jtag_tms valid after jtag_tck high
13.8
(1) Maximum cycle jitter supported by jtag _tck input clock.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
20
10
10
-2500
-1500
13.8
13.8
13.8
13.8
2500
1500
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 213
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