AM3517_16 Datasheet, PDF (100/223 Pages) Texas Instruments – AM3517, AM3505 Sitara™ Processors

AM3517, AM3505
SPRS550F – OCTOBER 2009 – REVISED JULY 2014
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5.9.4.2 DPLL Noise Isolation
The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise
generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the
cell to isolate it from substrate noise injection.
The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the
supply rails. The maximum input noise level allowed is 30 mV_PP for frequencies below 1 MHz.
Figure 5-10 shows an example of a noise filter.
DPLL_MPU
DPLL_CORE
DLL
DPLL5
DPLL4
Noise Filter
VDDS_DPLL_MPU_USBHOST
C
Noise Filter
VDDS_DPLL_PER_CORE
C
Figure 5-10. DPLL Noise Filter
030-017
Table 5-19 specifies the noise filter requirements.
Table 5-19. DPLL Noise Filter Requirements
NAME
MIN
TYP
Filtering capacitor
100
(1) The capacitors must be inserted between power and ground as close as possible.
(2) This circuit is provided only as an example.
(3) The filter must be located as close as possible to the device.
(4) No filtering required if noise is below 10 mV_PP.
MAX
UNIT
nF
5.10 Video DAC Specifications
A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary
control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one
per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the
video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-
11 shows the AM3517/05 DAC architecture.
100 Specifications
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