LMK04816_16 Datasheet, PDF (21/129 Pages) Texas Instruments – Three Input Low-Noise Clock Jitter Cleaner

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LMK04816
SNAS597C – JULY 2012 – REVISED JANUARY 2016
8.3 Feature Description
8.3.1 Serial MICROWIRE Timing Diagram
For timing specifications, see Timing Requirements. Register programming information on the DATAuWire pin is
clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire
signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is
recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire
signals must be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in
lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded
during this programming.
DATAuWire
MSB
D26 D25
D24
D23
D22
D0
A4
LSB
A1
A0
CLKuWire
LEuWire
t_ECS
t_DCS
t_CDH
t_CWH
t_CWL
t_CES
t_ECS
t_EWH
Figure 8. MICROWIRE Input Timing Diagram
8.3.2 Advanced MICROWIRE Timing Diagrams
8.3.2.1 Three Extra Clocks or Double Program
For timing specifications, see Timing Requirements. Figure 9 shows the timing for the programming sequence for
loading CLKoutX_Y_DIV > 25 or CLKoutX_Y_DDLY > 12 as described in Special Programming Case for R0 to
R5 for CLKoutX_Y_DIV and CLKoutX_Y_DDLY.
MSB
LSB
DATAuWire
D26
A0
CLKuWire
LEuWire
t_CES
t_ECS
t_CWL
t_CWH
t_EWH
Figure 9. MICROWIRE Timing Diagram: Extra CLKuWire Pulses for R0 to R5
8.3.2.2 Three Extra Clocks with LEuWire High
For timing specifications, see Timing Requirements. Figure 10 shows the timing for the programming sequence
which allows SYNC_EN_AUTO = 1 when loading CLKoutX_Y_DIV > 25 or CLKoutX_Y_DDLY > 12. When
SYNC_EN_AUTO = 1, a SYNC event is automatically generated on the falling edge of LEuWire. See Special
Programming Case for R0 to R5 for CLKoutX_Y_DIV and CLKoutX_Y_DDLY.
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