LMK04816_16 Datasheet, PDF (1/129 Pages) Texas Instruments – Three Input Low-Noise Clock Jitter Cleaner

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LMK04816
SNAS597C – JULY 2012 – REVISED JANUARY 2016
LMK04816 Three Input Low-Noise Clock Jitter Cleaner With Dual Loop PLLs
1 Features
•1 Ultralow RMS Jitter Performance
– 100-fs RMS Jitter (12 kHz to 20 MHz)
– 123-fs RMS Jitter (100 Hz to 20 MHz)
• Dual-Loop PLLATINUM™ PLL Architecture
– PLL1
– Integrated Low-Noise Crystal Oscillator
Circuit
– Holdover Mode When Input Clocks are Lost
– Automatic or Manual Triggering and
Recovery
– PLL2
– Normalized 1-Hz PLL Noise Floor of
–227 dBc/Hz
– Phase Detector Rate Up to 155 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO
– VCO Frequency Ranges From 2370 MHz
to 2600 MHz
• Three Redundant Input Clocks With LOS
– Automatic and Manual Switch-Over Modes
• 50% Duty Cycle Output Divides, 1 to 1045 (Even
and Odd)
• LVPECL, LVDS, or LVCMOS Programmable
Outputs
• Precision Digital Delay, Fixed or Dynamically-
Adjustable
• 25-ps Step Analog Delay Control, Up to 575 ps
• 1/2 Clock Distribution Period Step Digital Delay,
up to 522 Steps
• 13 Differential Outputs; up to 26 Single-Ended
– Up to 5 VCXO and Crystal-Buffered Outputs
• Clock Rates of Up to 2600 MHz
• 0-Delay Mode
• Three Default Clock Outputs at Power Up
• Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
• Industrial Temperature Range: –40°C to +85°C
• 3.15-V to 3.45-V Operation
• Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
1
2 Applications
• Data Converter Clocking and Wireless
Infrastructure
• Networking, SONET or SDH, DSLAM
• Medical, Video, Military, and Aerospace
• Test and Measurement
3 Description
The LMK04816 device is the industry's highest
performance clock conditioner with superior clock
jitter cleaning, generation, and distribution with
advanced features to meet next generation system
requirements. The dual-loop PLLATINUM architecture
enables 111-fs RMS jitter (12 kHz to
20 MHz) using a low-noise VCXO module or sub-
200-fs RMS jitter (12 kHz to 20 MHz) using a low-
cost external crystal and varactor diode.
The dual-loop architecture consists of two high-
performance phase-locked loops (PLL), a low-noise
crystal oscillator circuit, and a high-performance
voltage controlled oscillator (VCO). The first PLL
(PLL1) provides a low-noise jitter cleaner function
while the second PLL (PLL2) performs the clock
generation. PLL1 can be configured to either work
with an external VCXO module or the integrated
crystal oscillator with an external tunable crystal and
varactor diode. When used with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
noise (offsets below 50 kHz) of the VCXO module or
the tunable crystal to clean the input clock. The
output of PLL1 is used as the clean input reference to
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the far-
out phase noise (offsets above 50 kHz) where the
integrated VCO outperforms the VCXO module or
tunable crystal used in PLL1.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMK04816
WQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
Recovered
³GLUW\´ FORFN RU
clean clock
Backup
Reference Clock
IF
Crystal or
VCXO
CLKin0
OSCout0
CLKout0, 1
LMX2541
PLL+VCO
CLKin1
CLKin2
I
LMK04816
Precision Clock
Conditioner
CLKout2
CLKout3
CLKout4, 5, 6, 7
CLKout11
CLKout8A
F^FP^PG^GA^A
CLKout9
Q
CPLD
ADC
0XOWLSOH ³FOHDQ´
clocks at different
frequencies
Serializer/
Deserializer
D^DA^AC^C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.