LMK04816_16 Datasheet, PDF (18/129 Pages) Texas Instruments – Three Input Low-Noise Clock Jitter Cleaner

LMK04816
SNAS597C – JULY 2012 – REVISED JANUARY 2016
www.ti.com
Overview (continued)
8.1.7 Internal VCO
The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or
a divided version of the VCO for the clock distribution path. This same selection is also fed back to the PLL2
phase detector through a prescaler and N-divider.
The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd
divide values.
The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.
8.1.8 External VCO Mode
The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04816.
Using an external VCO reduces the number of available clock inputs by one.
8.1.9 Clock Distribution
The LMK04816 features a total of 12 outputs driven from the internal or external VCO.
All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or
LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 24
outputs are available.
If the buffered OSCin output OSCout0 is included in the total number of clock outputs the LMK04816 is able to
distribute, then up to 13 differential clocks or up to 26 single-ended clocks may be generated with the LMK04816.
The following sections discuss specific features of the clock distribution channels that allow the user to control
various aspects of the output clocks.
8.1.9.1 CLKout Divider
Each clock group, which is a pair of outputs such as CLKout0 and CLKout1, has a single clock output divider.
The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26
or greater are used, the divider an delay block uses extended mode.
The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in
normal mode instead of extended mode. This can result in a small current saving if enabling the VCO divider
allows 3 or more clock output divides to change from extended to normal mode.
8.1.9.2 CLKout Delay
The clock distribution section includes both a fine (analog) and coarse (digital) delay for phase adjustment of the
clock outputs.
The fine (analog) delay allows a nominal 25-ps step size and range from 0 to 475 ps of total delay. Enabling the
analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,
glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the
minimum-ensured maximum output frequency of 1536 MHz.
The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in
normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the
period of the clock distribution path by using the CLKoutX_Y_HS bit provided the output divide value is greater
than 1. For example, 2-GHz VCO frequency without using the VCO divider results in 250-ps coarse tuning steps.
The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.
There are 3 different ways to use the digital (coarse) delay.
1. Fixed Digital Delay
2. Absolute Dynamic Digital Delay
3. Relative Dynamic Digital Delay
These are further discussed in the Device Functional Modes.
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