LMH6401_16 Datasheet, PDF (21/48 Pages) Texas Instruments – LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier

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LMH6401
SBOS730A – APRIL 2015 – REVISED MAY 2015
Programming (continued)
9.5.2 Timing Diagrams
Figure 47 and Figure 48 show timing diagrams for the SPI write and read bus cycles, respectively. Figure 49 and
Figure 50 show timing diagrams for the write and read operations, respectively, of the LMH6401. Figure 51 and
Figure 52 illustrate example SPI stream write and read timing diagrams, respectively. Refer to the Electrical
Characteristics table for SPI timing requirements.
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDI
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
Figure 47. SPI Write Bus Cycle
CS
SCLK
SDI
SDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 48. SPI Read Bus Cycle
CS
SCLK
SDO
SDI
tPL
tPH
SCLK
tSU
tH
SDI
Valid Data
Figure 49. Write Operation Timing Diagram
tCSH tCSS
tCSH tCSS
1^st
Clock
8^th
Clock
15^th
Clock
tOZD
Hi-Z
tOD
tODZ
Valid
Valid
Valid
Data
Data
Data
Valid
Hi-Z
Data
Figure 50. Read Operation Timing Diagram
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