LMH6401_16 Datasheet, PDF (20/48 Pages) Texas Instruments – LMH6401 DC to 4.5 GHz, Fully-Differential, Digital Variable-Gain Amplifier

LMH6401
SBOS730A – APRIL 2015 – REVISED MAY 2015
www.ti.com
9.3 Feature Description
The LMH6401 includes the following features:
• Fully-differential amplifier
• Digitally-controlled variable gain: –6 dB to 26 dB in 1-dB steps
• Output common-mode control
• Single- or split-supply operation
• Large-signal bandwidth of 4.5 GHz
• Usable bandwidth up to 2 GHz
• Power-down control
9.4 Device Functional Modes
9.4.1 Power-On Reset (POR)
The LMH6401 has a built-in, power-on reset (POR) that sets the device registers to their default state (see
Table 3) on power-up. Note that the LMH6401 register information is lost each time power is removed. When
power is reapplied, the POR ensures the device enters a default state. Power glitches (of sufficient duration) can
also initiate the POR and return the device to a default state.
9.4.2 Power-Down (PD)
The device supports power-down control using an external power-down (PD) pin or by writing a logic high to bit 6
of SPI register 2h (see the Register Maps section). The external PD is an active high pin. When left floating, the
device defaults to an on condition when the PD pin defaults to logic low as a result of the internal pulldown
resistor. The device PD thresholds are noted in the Electrical Characteristics table. The device consumes
approximately 7 mA in power-down mode. Note that the SPI register contents are preserved in power-down
mode.
9.4.3 Thermal Feedback Control
The LMH6401 has a thermal feedback gain and frequency control feature that allows for improved low-frequency
settling performance. The Thermal Feedback Gain Control and Thermal Feedback Frequency Control registers
set through the SPI control this feature. The default setting is described in Table 3. Graphs are Included in the
Application and Implementation section that illustrate how the thermal feedback gain and frequency control
allows for enhanced performance.
9.4.4 Gain Control
The LMH6401 gain can be controlled from 26-dB gain (0-dB attenuation) to –6-dB gain in 1-dB steps by digitally
programming the SPI register 2h. See the Register Maps section for more details.
9.5 Programming
9.5.1 Details of the Serial Interface
The LMH6401 has a set of internal registers that can be accessed by the serial interface controlled by the CS
(chip select), SCLK (serial interface clock), SDI (serial interface input data), and SDO (serial interface readback
data) pins. Serial input to the device is enabled when CS is low. SDI serial data are latched at every SCLK rising
edge when CS is active (low). Serial data are loaded into the register at every 16th SCLK rising edge when CS is
low. When the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in
multiples of 16-bit words within a single active CS pulse. The first eight bits form the register address and the
remaining eight bits form the register data. The interface can function with SCLK frequencies from 50 MHz down
to very low speeds (of a few Hertz) and also with a non-50% SCLK duty cycle. A summary of the LMH6401 SPI
protocol follows:
• SPI-1.1 compliant interface
• SPI register contents protected in power-down
• SPI-controlled power-down
• Powered from the main VS+ power supply
• 1.8-V logic compliant
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