CDCE813-Q1 Datasheet, PDF (21/29 Pages) Texas Instruments – Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs

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Typical Application (continued)
CDCE813-Q1
SNAS705 – JANUARY 2017
Figure 16. Crystal Oscillator Start-Up vs PLL Lock Time
10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
The frequency for the CDCE813-Q1 device is adjusted for media and other applications with the VCXO control
input V_ctr. If a PWM-modulated signal is used as a control signal for the VCXO, an external filter is needed.
LP
Vctrl
CDCE813-Q1
PWM
control
signal
Xin/CLK
Xout
Copyright © 2017, Texas Instruments Incorporated
Figure 17. Frequency Adjustment Using PWM Input to the VCXO Control
10.2.2.5 Unused Inputs and Outputs
If VCXO-pulling functionality is not required, V_ctr should be left floating. All other unused inputs should be set to
GND. Unused outputs should be left floating.
If one output block is not used, TI recommends disabling it. However, TI recommends providing a supply for all
output blocks, even if they are disabled.
10.2.2.6 Switching Between XO and VCXO Mode
When the CDCE813-Q1 device is in the crystal-oscillator or VCXO configuration, the internal capacitors require
different internal capacitance. The following steps are recommended to switch to VCXO mode when the
configuration for the on-chip capacitor is still set for XO mode. To center the output frequency to 0 ppm:
1. While in XO mode, put V_ctr = V_DD / 2
2. Switch from XO mode to VCXO mode
3. Program the internal capacitors to obtain 0 ppm at the output.
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: CDCE813-Q1
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