CDCE813-Q1 Datasheet, PDF (20/29 Pages) Texas Instruments – Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs

CDCE813-Q1
SNAS705 – JANUARY 2017
www.ti.com
Typical Application (continued)
10.2.2.2 PLL Frequency Planning
At a given input frequency (f_IN), the output frequency (f_OUT) of the CDCE813-Q1 device is calculated with
Equation 1.
ƒ_OUT
=
ƒ_IN
Pdiv
´
N
M
• M (1 to 511) and N (1 to 4095) are the multiplier or divider values of the PLL,
• and Pdiv (1 to 127) is the output divider.
(1)
The target VCO frequency (ƒ_VCO) of each PLL is calculated with Equation 2.
ƒ_VCO
=
ƒ_IN
´
N
M
(2)
The PLL internally operates as fractional divider and needs the following multiplier or divider settings:
•N
• P = 4 – int(log₂N / M); if P < 0 then P = 0
• Q = int(N' / M)
• R = N′ – M × Q
where
• int(X) = integer portion of X
• N′ = N × 2^P
• N≥M
80 MHz ≤ ƒ_VCO ≤ 230 MHz
16 ≤ Q ≤ 63
0≤P≤4
0 ≤ R ≤ 51
Example:
for ƒ_IN = 27 MHz; M = 1; N = 4; Pdiv = 2
→ f_OUT = 54 MHz
→ f_VCO = 108 MHz
→ P = 4 – int(log₂4) = 4 – 2 = 2
→ N' = 4 × 2² = 16
→ Q = int(16) = 16
→ R = 16 – 16 = 0
for ƒ_IN = 27 MHz; M = 2; N = 11; Pdiv = 2
→ f_OUT = 74.25 MHz
→ f_VCO = 148.50 MHz
→ P = 4 – int(log₂5.5) = 4 – 2 = 2
→ N' = 11 × 2² = 44
→ Q = int(22) = 22
→ R = 44 – 44 = 0
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.
10.2.2.3 Crystal Oscillator Start-Up
When the CDCE813-Q1 device can be used as a crystal buffer, the crystal oscillator start-up dominates the start-
up time compared to the internal PLL lock time. Figure 16 shows the oscillator start-up sequence for a 27-MHz
crystal input with an 8-pF load. The start-up time for the crystal is on the order of approximately 250 µs
compared to approximately 10 µs of lock time. In general, lock time is an order of magnitude less compared to
the crystal start-up time.
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