CDCE813-Q1 Datasheet, PDF (1/29 Pages) Texas Instruments – Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs

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CDCE813-Q1
SNAS705 – JANUARY 2017
CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner
With 2.5-V and 3.3-V Outputs
1 Features
•1 Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2: –40°C to 105°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C6
• In-System Programmability and EEPROM
– Serial Programmable Volatile Register
– Nonvolatile EEPROM to Store Customer
Settings
• Flexible Input Clocking Concept
– External Crystal: 8 MHz to 32 MHz
– Single-Ended LVCMOS up to 160 MHz
• Free Selectable Output Frequency up to 230 MHz
• Low-Noise PLL Core
– PLL Loop Filter Components Integrated
– Low Period Jitter (Typical 50 ps)
• 1.8-V Device Power Supply (Core Voltage)
• Separate Output Supply Pins
– CDCE813-Q1: 3.3 V and 2.5 V
• Flexible Clock Driver
– Three User-Definable Control Inputs [S0, S1,
S2], for Example, SSC Selection, Frequency
Switching, Output Enable, or Power Down
– Generates Highly Accurate Clocks for Video,
Audio, USB, IEEE1394, RFID, Bluetooth^®,
WLAN, Ethernet, and GPS
– Generates Common Clock Frequencies Used
With TI-DaVinci™, OMAP™, DSPs
– Programmable SSC Modulation
– Enables 0-PPM Clock Generation
• Packaged in TSSOP
• Development and Programming Kit for Easy PLL
Design and Programming (TI Pro-Clock™)
2 Applications
• Cluster
• Head Unit
• Navigation Systems
• Advanced Driver Assistance Systems (ADAS)
3 Description
The CDCE813-Q1 device is a modular Phase-locked-
loop-based (PLL), low-cost, high-performance,
programmable clock synthesizers. They generate up
to three output clocks from a single input frequency.
Each output can be programmed in-system for any
clock frequency up to 230 MHz, using the integrated
configurable PLL.
The CDCE813-Q1 has separate output supply pins,
V_DDOUT, providing 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS
clock signal. A selectable on-chip VCXO allows
synchronization of the output frequency to an external
control signal.
The PLL supports SSC (spread-spectrum clocking)
for better electromagnetic interference (EMI)
performance.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDCE813QPWRQ1 TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
PCLK
CDCE813-Q1
I2C
SoC
Image Data
Serializer
To Display
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.